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Multisim/verilog question

  1. Mar 9, 2013 #1
    Hello,
    I just started learing verilog and i have 2 problems.
    First one, i cant find an useful documentation on internet which might help me to solve my homework.
    Second one, its the homework :D.
    I have to make a program in verilog which calculates the difference between 2 numbers of 16 bits.
    The problem is that i dont know how to test my design, i did try to put a=305, b=540 but when i run it (simulate-add to wave-run ) i dont see the binary signal, it shows me somthing green with this text inside 16`h0000. Can you tell me the right way to initiate the variables???
    My code:
    Code (Text):
    module Difft;
      reg [15:0]a;
      reg [15:0]b;
      wire [15:0]c;
      initial begin
        a=0;
        b=0;
        #2 a=70;
        b=35;
      end
      Diff DUT(.a(a),.b(b),.c(c));
    endmodule
     
    Code (Text):

    module Diff(input [15:0]a,input [15:0]b,output [15:0] c);
      assign c=a-b;
    endmodule
     
     
  2. jcsd
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