I started Digital Logic this Spring at Uni and was generally thinking that is it possible to directly change a nand circuit to a nor circuit without making it again from the start,when i mean making a circuit I mean implementing it on paper not practically! Like suppose we have a function in SOP form F=B'C'+A'C"+A'B' and I can implement it using NAND gates fine but what if I want to change that circuit directly into NOR how do I do that?
I did see that.I know how to convert a schemetic made with simple OR,NOR and AND gates into NAND and NOR using the bubble logic but what if I want to change a schemetic made with NAND into NOR will that be done using bubbles too? if yes then how?
You can implement the NAND function using only NOR gates. De Morgan says (x.y)' = x' + y' But when an OR gate is not available, use NOR then invert its output using another NOR as an inverter. = ( (x' + y')' )'
But suppose a schmetic is implemented using NAND gates how would I place the bubbles so that it automatically changes into NOR without redrawing the schematic? I know NAND=OR with inverted inputs and NOR=AND with inverted inputs
I thought that was precisely what I just showed. Sorry, uknowwho. Of the three questions you have asked in this thread, I haven't been able to understand even one. I took a stab and answered what I thought could be a likely question. It seems I didn't guess right.
So as OR = NOR with inverted output, NAND = NOR with inverted inputs and output. Using the fact that NOT = NOR with inputs joined you can therefore replace every NAND gate with four NOR gates. There will be a lot of redundant back-to-back inverters in this circuit which can be eliminated.
Okay what I originally did was that I assumed the AND's which we got from NAND gates and inverted their inputs as NOR=AND with inverted inputs and just inverted the OR gates formed with the NAND gates so that they become NOR so i guess that was wrong Do I have to put invertors(bubbles) infront of the inputs and outputs of both the NAND's which were used to form the AND gate? You can see the orginal schemtic which I did
I think you need to revise your understanding of a couple of things: The 'bubbles' that are part of the symbols for NAND and NOR gates are just part of the symbols for the respective components - you can't "draw them in" on inputs (otherwise you are specifying a different component which you haven't got access to and may not even be manufactured). If you want to invert a signal, you use an invertor, also called a NOT gate. NOT gates can be implemented by joining the inputs of either a NAND gate or a NOR gate, but you cannot implement a NOT gate with an AND or OR (or XOR) gate - look at the truth tables to understand why. This means that you can construct ANY logic circuit using only NAND gates, or only NOR gates, but not using only AND, OR or XOR gates. Your circuit with the NAND gates has two NAND gates connected in series, each with their inputs joined. What is the output from this section of circuit when the input is 1? And when the input is 0? If you want to build this circuit with NOR gates you might like to start with the fact that A'B' = (A + B)' and so can be implemented with a single NOR gate, although you will get to the same result by replacing the NANDs with 4 NORs and eliminating the series inverters.
I do get the De Morgan's Law but The question we were given was that how to implement the circuit made with NAND gates into NOR gates directly and we were given the hint of using bubbles to invert the circuits..Is it possible you can draw it out to give an example. I'm sure I'll get it then. I really need to understand it, it would be a huge help
Well (i) I don't have any easy means of posting a sketch at the moment and (ii) I'm not going to do it for you anyway, you need to do it yourself. But I will help. First of all there are 6 redundant gates in this circuit - eliminate them. Then replace every NAND gate with a NOR gate with each input and output connected through an inverter - or if you like, draw bubbles on each input and output (the output will therefore have two bubbles). Now you can simplify this circuit: wherever a bubble on an output connects to a bubble on an input, elminate them both. Note that you can only do this with the extra bubble on the outputs because one bubble is part of the circuitry of the NOR gate. Also where an inverter connects to a bubble, or a bubble to an inverter, eliminate them both. Your answer should have a total of 7 NOR gates, 2 of them wired as inverters. The effecient solution with NAND gates had a total of 9, 4 of them wired as inverters. This problem may be used to illustrate engineering efficiencies - if building a production run of this circuit using standard componenents, 9 NAND gates would require 3 packages (quad 2 input NAND) whereas 7 NOR gates would only require 2 (quad 2 input NOR). But the optimum solution would use 2 3-input NORs and an inverter, which are available in a single package (CMOS 4000 or 4025).