1. Not finding help here? Sign up for a free 30min tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Need help with declaration!

  1. Jul 25, 2011 #1
    library ieee;
    use ieee.std_logic_1164.all;
    entity miniproject is
    port (dg1, dg2 : in std_logic_vector (3 downto 0);
    led1, led2 : out std_logic_vector ( 6 downto 0);
    output :eek:ut std_logic(6 downto 0));
    end miniproject;
    architecture arc of miniproject is
    begin
    with dg1 select
    led1 <= "0010010" when "0010",
    "1001100" when "0100",
    "1111111" WHEN others;
    with dg2 select
    led2<= "0010010" when "0010",
    "1001100" when "0100",
    "1111111" WHEN others;


    process( dg1,dg2 )
    begin
    if (dg1 = "0010" and dg2 = "0000") then
    led1 <= '0' ; led2 <= '0' ;
    elsif (dg1 = "0100" and dg2 = "0000") then
    led1 <= '0' ; led2 <= '0' ;
    else
    led1 <= '1'; led2 <= '1';
    end if;
    end process;
    end arc;

    Error (10380): VHDL error at miniproject.vhd(6): std_logic type is used but not declared as an array type
    Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
    Error: Processing ended: Tue Jul 26 09:21:14 2011
    Error: Elapsed time: 00:00:02
     
  2. jcsd
  3. Jul 25, 2011 #2
    The programme I want to do is using 8 inputs which represent 2 digits from 00 -99. Using 7- segments displays and Led1 and Led2 will light up when the values are "20" and "40". Hope you can help me.
     
  4. Jul 25, 2011 #3
    Need help with my lab!

    Question: 8 inputs are used to represent 2 digits from 00 to 99. Show the value on the 7-segment displays and the Led1 and Led2 will light up when the values are “20” and “40” respectively.

    My answer:
    library ieee;
    use ieee.std_logic_1164.all;
    entity miniproject is
    port (dg1, dg2 : in std_logic_vector (3 downto 0);
    led1, led2 : out std_logic_vector ( 6 downto 0);
    output :eek:ut std_logic(6 downto 0));
    end miniproject;
    architecture arc of miniproject is
    begin
    with dg1 select
    led1 <= "0010010" when "0010",
    "1001100" when "0100",
    "1111111" WHEN others;
    with dg2 select
    led2<= "0010010" when "0010",
    "1001100" when "0100",
    "1111111" WHEN others;


    process( dg1,dg2 )
    begin
    if (dg1 = "0010" and dg2 = "0000") then
    led1 <= '0' ; led2 <= '0' ;
    elsif (dg1 = "0100" and dg2 = "0000") then
    led1 <= '0' ; led2 <= '0' ;
    else
    led1 <= '1'; led2 <= '1';
    end if;
    end process;
    end arc;

    Error (10380): VHDL error at miniproject.vhd(6): std_logic type is used but not declared as an array type
    Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
    Error: Processing ended: Tue Jul 26 09:21:14 2011
    Error: Elapsed time: 00:00:02




    What is wrong? can anyone help me?? THX in advance. (If possible Help me edit)
     
  5. Jul 25, 2011 #4

    jtbell

    User Avatar

    Staff: Mentor

    Just out of curiosity, what language is this? I don't recognize it.

    [added] OK, I see from the error message that it's VHDL. Carry on...
     
  6. Jul 26, 2011 #5
    Re: Need help with my lab!

    Perhaps you need to use "std_logic_vector" instead of "std_logic" in line 6 as you did in lines 4 and 5.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook




Similar Discussions: Need help with declaration!
  1. Need Help (Replies: 2)

  2. Help needed (Replies: 1)

  3. Need help! (Replies: 14)

Loading...