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NMOS Loaded NMOS inverter

  1. Sep 19, 2015 #1
    1. The problem statement, all variables and given/known data
    NMOS%20inverter_zpshjemzera.png
    Given
    Vdd = 5v, Vgg = 10v, Kn' = 20uA/V^2 (For both transistors), (W/L)o = 10um/5um, (W/L)L = 5um/20um, Vt = 1.1V (for both)

    My question is what would be the Vgd, and Vgs of the load NMOS?
    2. Relevant equations
    upload_2015-9-19_12-50-11.png


    3. The attempt at a solution
    So far, what i have is:
    The NMOS Load is always in linear mode. Id = Kn[(Vgsl – Vt)Vdsl – 0.5*Vdsl^2]

    Vi = Vgso

    Vo = Vdso
     
  2. jcsd
  3. Sep 20, 2015 #2

    rude man

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    (W/L)o = 10um/5um, (W/L)L = 5um/20um
    What are these?


    Kn' = 20uA/V^2
    Why Kn'? why the prime?

     
  4. Sep 20, 2015 #3
    The W/L is the width over the length of the channel of the transistors. Basically Kn = Kn'*W/L
     
  5. Sep 20, 2015 #4

    rude man

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    which is which? does "o" stand for the upper and "L" for the lower transistor?
    also need to know Vi.
     
  6. Sep 20, 2015 #5
    The O is the lower transistor, the L is the upper transistor (L for Load)
     
  7. Sep 20, 2015 #6

    rude man

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    Vi?
     
  8. Sep 20, 2015 #7
    Vi would be variable, from 0 to Vdd
     
  9. Sep 20, 2015 #8
    The original question to this problem is to re-create its VTC curve and find all of the critical points of the VTC (Vm, Voh, Vol, Vih, Vil, NMh, NML, and power dissipation
     
  10. Sep 20, 2015 #9

    rude man

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    It can vary all the way from 0V to 5V? That would make the problem a tall order. Do you have pspice? :smile:

    Or maybe Vi is either 0V or 5V? That we could live with ...
     
  11. Sep 20, 2015 #10
    Yes, if we look at the extremes it would help
     
  12. Sep 20, 2015 #11

    rude man

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    OK. Because if you allow the entire range from 0 to 5V one or both devices will transition from one mode to another, making for a headache unless you do it with some kind of software. You could use spice or write your own high-level-language program.
    Also, your statement that the load FET is always in the linear mode is incorrect sice there is effectively nothing connected to its source if Vi = 0.
    Stay tuned.
     
  13. Sep 20, 2015 #12
    I simulated the circuit exactly as described
    https://goo.gl/photos/bHLqKvAJKTMKLym86

    It seems Voh=5v
    Vol=1v
    Vm = 2.5v

    This is all according to simulation, would this be close to what the theoretical should be
     
  14. Sep 20, 2015 #13

    rude man

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    I will try to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
    EDIT: instead I will give you suggestions on how to proceed:
    1. You have the L fet always in the linear mode, as you say.
    2. assume the o fet is also in the linear mode. Equate the two fets' equations since the current is the same. Solve for all voltages. If the voltages meet the requirements for the linear mode for the o fet, you're done.
    3. if not, then assume the o fet is in the saturated mode and repeat solving for all the voltages the same way.
    For Vi = +2.5V and +5V the o fet has to be in either the linear or saturated mode.
    For Vi = +1V it should be obvious what the mode of the o fet is.
    Your simulation looks about right.
    Remember you have Vd1 = Vs2 etc. The only unknown is Vd1 = Vs2.
    P.S. an excel spreadsheet might be a good way to do this.
     
    Last edited: Sep 20, 2015
  15. Sep 20, 2015 #14
    So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
     
  16. Sep 21, 2015 #15

    rude man

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  17. Sep 21, 2015 #16

    rude man

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    You mean QL, not "the O transistor", right? To avoid further confusion, I am using the subscript "1" for Qo and "2" for QL henceforth:
    You have every voltage except Vd1 which is also Vs2:
    Vg1 = Vi (i.e. 1V, 2.5V and/or 5v)
    Vg2 = +10V
    Vd2 = +5V
    Vs1 = 0
    So, solve for Vd1 which is also Vs2.
     
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