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NOT gate feedback

  1. Mar 11, 2008 #1
    If I have a simple TTL NOT gate and had a feedback line from the output to the input, then how would I explain what happens to the output voltage for certain inputs?
    Does it just simply oscillate continuously?
     
  2. jcsd
  3. Mar 11, 2008 #2

    rbj

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    yeah, it does. but if you want a little self-taught lesson in the the conceptuallization of 1 bit of static memory, you might want to ask yourself what would happen if it were two NOT gates in series and you feed the output back into the input. then what do you get?
     
  4. Mar 11, 2008 #3
    Thats pretty cool - the double gate would just store a single bit.
    But with my original question, what would happen if you put a multimeter on it - I assume its oscillating too fast to be detected?
     
  5. Mar 11, 2008 #4
    that would be up to the switching speed of the device.

    would need an oscilloscope to really see the effect
     
  6. Mar 11, 2008 #5

    rbj

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    sorry for continuing to diverge from the original question (it's not very interesting, of course it would oscillate and very quickly), but now that you can see that 2 NOT gates in a loop can be stable with either a 1 or a 0 at the output of the 2nd gate which is the same as the input to the first gate. now, how would you revise the circuit so that you can force the output to be 1 or 0 before allowing for that value to be saved? if you follow this and replace the NOT gates with either NOR oe NAND gates, you will see you have an RS flip-flop. add a little more and you have a D flip-flop. add a little more and you have a master-slave D flip-flop (that's pretty much what a single bit of static memory is).
     
  7. Mar 12, 2008 #6

    berkeman

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    Staff: Mentor

    A simple CMOS inverter with the output connected to the input is biased in the linear region, and the output and input will generally hold near mid-rail. It takes some reactive impedance to get the inverter to oscillate, like in figure 4 in the following datasheet for the 74HCU04:

    http://www.onsemi.com/pub_link/Collateral/74HCU04.REV0.PDF
     
  8. Mar 12, 2008 #7
    How does the biasing in the linear region imply that the voltage will "hold near mid-rail"? Aren't most gates (TTL/CMOS) all biased in the linear region anyway?
    Also, doesn't the reactive impedance just set the oscillation frequency rather than the rapid oscillation it may intrinsically do?
     
  9. Mar 12, 2008 #8

    berkeman

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    Staff: Mentor

    No, digital gates operate in the saturated region and cutoff region of the constituent transistors. So if the input of an inverter gate is low, then the output pullup transistor is saturated (on), and the pulldown transistor is cutoff (off). When the input transitions low-to-high, after the input passes the crossover point, the output transistors snap the other way.

    But if you tie the output back to the input, you get basically a configuration similar to an opamp where you tie the output back to the "-" input, which is a follower. But there is no "+" input to the gate in this configuration to follow, so the configuration is generally marginally stable, with the bias point stabilizing mid-rail for both output and input. But there is a moderate amount of gain there, so if there is a phase shift introduced between output and input (like with the reactive impedance of the crystal oscillator circuit), and there is a tiny bit of perturbing noise to start the oscillation, then you can get an amplitude-limited oscillation at the resonant frequency of the crystal, and hence the classic crystal oscillator based on an (unbuffered, usually) inverter gate.
     
  10. Mar 12, 2008 #9
    Thanks berkeman - that all makes sense and I'm back to being happy.
     
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