# NPN Transistors

Hey guys, was just wondering if you could clear up a fact about NPN transistors.

1. Is this emmiter current slightly larger than the collector current?
2. The reason why the emmiter current is slightly larger is because the emitter current is a combination of the collector current plus the current in the base?
3. By placing a capacitor in a simply amplifying circuit with an NPN transistor, it causes the signal to come out un-inverted? (sorry, couldnt think of a better word for it )

Any explanations to how an NPN transistor works would be most appreciated!!!

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(1) yes
(2) Correct, Ie = Ic + Ib
(3) if you mean the "coupling capacitor" connected to the output of an amplifier stage, no - it doesn't invert or uninvert anything. It's there because you want to transmit only the oscillating signal to the next circuit, you don't want to transmit the DC level that the signal is sitting on top of. A capacitor is an open circuit to DC. If you have a voltage that's the sum (A + B cos omega t), and you want to throw away the (A) and keep only the (B cos omega t), you make your connection through a series capacitor. However, that will make the signal drop off toward zero for very low frequencies.

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I thought the capacitor must have that effect but doesnt it invert the output signal? In my text book ive got an ordinary npn amplifier circuit which was a capacitor at Vin and another at Vout. My text states "By adding two coupling capacitors, the simple transistor circuit can be converted to an inverting amplifier."

I thought the capacitor must have that effect but doesnt it invert the output signal? In my text book ive got an ordinary npn amplifier circuit which was a capacitor at Vin and another at Vout. My text states "By adding two coupling capacitors, the simple transistor circuit can be converted to an inverting amplifier."
If you use two OUTPUT coupling capacitors, one connected to the collector and another connected to the emitter, one will have an inverted output and one will be in phase with the incoming signal.

I think they mean one coupling capacitor at the base (input) and one coupling capacitor at the collector (output).

The capacitors aren't what inverted the signal. What inverted the signal is the fact that when the base is high the collector is low; when the base is low the collector is high.

Yer thats what i was about to say mikelepore. But if the capacitors arent there, the signal isnt inverted right?

And what would be the effect if in circuit A there was a capacitor at the base and in circuit B there was a capacitor at the collecter?

And what would be the effect if in circuit A there was a capacitor at the base and in circuit B there was a capacitor at the collecter?
A picture is worth a thousand words...

here's your basic common emitter capacitor-coupled circuit: http://www.tpub.com/neets/book7/25c.htm
The output signal is inverted.

However, the common base or common collector does not invert the signal.
http://www.tpub.com/neets/book7/25f.htm

The insertion of a capacitor will not affect the phase.

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Yer thats what i was about to say mikelepore. But if the capacitors arent there, the signal isnt inverted right?
The signal is inverted regardless of whether the output coupling capacitor is there or not. It only requires that the circuit is biased correctly with resistors. The moment when the base voltage is maximum will be the same moment when the collector voltage will be minimum. That's an inversion. (In fact, logic gates don't use such coupling capacitors. A trassistor can be used as a binary inverter.)

But if the capacitor is removed, you won't have a proper signal for the next stage to receive. You want the next stage to have its quiescent point set carefully by its own resistor, not messed up by the previous stage. You want only a sinusoid to get fed to the next stage.

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Ahere's your basic common emitter capacitor-coupled circuit: http://www.tpub.com/neets/book7/25c.htm
Thanks for posting the link to that picture. Looking at the picture, I think it will help Sanado to visualize: at a moment when when the base voltage and current are maximum, that will be the moment when C-E junction is conducting, the C-E voltage is minimum. At that moment, the maximum percentage of the power supply voltage V_CC will be across the load resistor R_L rather than across the C-E junction.

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Thanks for posting the link to that picture. Looking at the picture, I think it will help Sanado to visualize: at a moment when when the base voltage and current are maximum, that will be the moment when C-E junction is conducting, the C-E voltage is minimum. At that moment, the maximum percentage of the power supply voltage V_CC will be across the load resistor R_L rather than across the C-E junction.
Yea, I was a bit confused by his statement. It seemed to imply that the capacitors were responsible for the inversion, and my reply was simply to indicate that it depends on the configuration (ie. common collector or common emitter) and not the insertion of a capacitor.

By making connections to both the collector and the emitter, he could have an inverting and non-inverting output (assuming the proper resistors were inserted).

No joke, this has to be the hardest thing i have ever studied. After reading those links provided, i've suddenly realized i am clueless about how an NPN transistor works. First of all, in the link http://www.tpub.com/neets/book7/25c.htm in figure 2-12.,

1. Ive always assumed that RL and Rb where simply the internal resistance of each part of the NPN transistor, not separate resistors.

2. RL prevents current flowing into the collector? If this is the case, why would you even connect that part of the circuit together, simply save a resistor.

3. Why exactly does the signal get inverted, i just dont understand the explanation that is provided in that link?

4. Why does saturation occur?

No joke, this has to be the hardest thing i have ever studied. After reading those links provided, i've suddenly realized i am clueless about how an NPN transistor works. First of all, in the link http://www.tpub.com/neets/book7/25c.htm in figure 2-12.,

1. Ive always assumed that RL and Rb where simply the internal resistance of each part of the NPN transistor, not separate resistors.

2. RL prevents current flowing into the collector? If this is the case, why would you even connect that part of the circuit together, simply save a resistor.

3. Why exactly does the signal get inverted, i just dont understand the explanation that is provided in that link?

4. Why does saturation occur?

5. The resistor just before the B-E junction, that is responsible for forward biasing the transistor and setting the quiescent point?

6. The new signal, does it have a DC compensate and a AC compensate, or is it simply a larger version of the input signal?

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First, RB limits (but doesn't prevent) current flowing into the base, and provides the required bias to overcome the quiescence of the transistor, 'turning it on'.

Next, RL limits current flow into the collector. A voltage develops across RL that is in direct proportion to the value of the resistor and the current flowing through the resistor (ohms law).

Now that the transistor is 'on', direct current flows through RL and the junctions of CB and BE to ground. With the correct RB resistance, base bias will result in the output waveform indicating 'zero' voltage. The transistor is now saturated and maximum current flows through the device, limited only by RL and the internal resistance of the transistor itself.

And, when a signal is applied to the base (with or without a capacitor), negative voltage on the base brings the transistor out of saturation. The collector output voltage will begin to rise in direct proportion to the applied base input voltage, but 180 degrees out of phase.

Finally, as the input signal to the base becomes 'positive' again, the process goes the other way- the collector current increases (and the voltage decreases)- the transistor becomes saturated again.

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