Odd parity checker using Verilog

  1. 1. The problem statement, all variables and given/known data

    In this assignment, we will learn how to model flip-flops in the Verilog language and we will use a D flip-flop to construct a simple state machine. Our state machine will act as an “odd parity checker”, a state machine whose output is 1 when it observes an odd number of 1’s at its input since the last reset, and 0 when it has observed an even number of 1’s at its input. The transition equation for such a machine is straight-forward, Q* = Q ^ D, where D is the input being observed, Q is the present state, and Q* is the next state. The output of this state machine is simply Q.

    Add a Verilog source file named “parity.v”, and create a module named “parity (clk, reset, d, q)”, with inputs and outputs as in the D flip-flop. Design and enter the description of a circuit that acts as an “odd parity” checker using an instance of the “dff” module from Step 1 (see below).
    Verify that the syntax is correct, and compile your Verilog module.



    2. Relevant equations



    3. The attempt at a solution
    Here is what I have for the dff module and its been tested and works

    module dff (clk,reset,d,q);
    input clk,reset,d;
    output reg q;

    always @ (posedge clk or posedge reset) if (reset) q = 0; else q = d;

    endmodule


    I dont understand how to make the "odd parity module". I'm confused by the definition: does it mean have q output 1 when clk, reset and d combined have a odd number of 1s?

    How does the transition equation Q* = Q ^ D fit in with this

    HELP!!
     
  2. jcsd
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