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Opamp design

  1. Oct 2, 2009 #1
    1. how can i modify the circuit to get a gain of 4000 and 9000? how should i start?
    2. how to replace the current source in practical, i.e in lab.?
    3. to get such a high gain the rc1 seem has to replaced with active load.but what is meant by active load and how to build it?
    thanks.:smile:
     

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  2. jcsd
  3. Oct 2, 2009 #2

    uart

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    - Active load means current source (replace rc1 with Ic1 current source)

    - current source (approx) is constructed using current mirrors.

    - current mirrors for Ie and for Ic1 should be linked. Using area-ratio matching (or two transistors in parallel for Ie) you can make Ie two times Irc1.


    *** Is this homework - it looks like homework. ***
     
    Last edited: Oct 3, 2009
  4. Oct 2, 2009 #3
    this is not a homework,but a lab experiment.the lecturer want us to design an op amp with gain 4000 with that circuit.but we haven't study about any thing about active load nor current mirror.can u draw the circuit to obtain gain of 4000?maybe i can learn from your circuit.because now even now i don't know how to start.
     
  5. Oct 3, 2009 #4

    berkeman

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    This is indeed homework/coursework, but so far I'm going to let it stay here in EE. (prescott, please re-read the Rules link at the top of the page.)

    Designing an opamp subject to various constraints is standard EE upper-division coursework, and is usually pretty challenging. The usual homework/coursework help guidelines apply -- the original poster (OP) needs to do the bulk of the work. We can provide tutorial hints and corrections, but not much else.

    So prescott, what main mechanisms do you have to control the gain? What are the risks of increasing the gain without doing some other house-keeping?
     
  6. Oct 4, 2009 #5
    i have arrive with the circuit above.can you teach me how to replace the current source with real circuit?and show me the connection to measure open loop gain.

    circuit source: Ron H from allaboutcircuits.com
     

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    Last edited: Oct 4, 2009
  7. Oct 4, 2009 #6

    uart

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    Ok that's good. The "active load" is basically just a current mirror. Use a similar current mirror for Ie. See for exmaple : http://en.wikipedia.org/wiki/Current_mirror

    Before you go any further you should consider what other characteristics your opamp should have and use this to help you choose values for Ie and RC2. Did you have any other target specifications, like input bias current or input resistance or minimum load resistance for specified gain?

    Do you have any values in mind for Ie and RC2?

    BTW. Once you get the hang of curent mirrors you might want to consider also replacing RC2 with a current source to improve the gain and increase available the output signal swing.
     
  8. Oct 4, 2009 #7

    uart

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    First you need to identify which is the inverting and which is the non-inverting input.

    Open loop is just the input to output gain without any feedback. So just connect the inverting input to ground and connect a signal to the non-inverting input. You may need to include to DC offset adjustment to make open loop measurement. This could be as simple as using a potentiometer to place a small DC voltage (instead of ground) at the inverting input for example.
     
  9. Oct 4, 2009 #8
    sorry,what you mean by Ie?do you mean Iq(the current source)?nope,my lecturer just ask us to modify the circuit to obtain a gain of 4000.he does not specify anything else,maybe he want us to assume all thing ourselves.so what should i proceed to obtain the current source circuit?
    back to open loop gain,so i only connect ac source (0.1V 1kz) to +ve input then ground -ve input,and measure Vo ,then the result divide by 0.1V?by the way,where is the Vo?is it at the node between q4 and q5?
     
  10. Oct 4, 2009 #9

    uart

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    "sorry,what you mean by Ie?do you mean Iq(the current source)?"
    Whoops, yes I meant Iq. :eek:

    "nope,my lecturer just ask us to modify the circuit to obtain a gain of 4000.he does not specify anything else,maybe he want us to assume all thing ourselves."
    Ok then that makes it a bit easier. Larger values of Iq will give you higher gain but lower input resistance (and higher bias currents).

    See if you can get it working with Iq say around 200uA, this will keep the bias curernts down around 1uA or better and will probably get the input resistance somewhere up around 10k. A true opamp would of course be a lot better than this but these figures would probably be considered ok for that circuit.
     
  11. Oct 4, 2009 #10
    i connect like what you say.but the gain only 100.is my connection in the circuit correct?or wrong in some part?is Vo the node between q4 and q5?
     

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  12. Oct 4, 2009 #11

    uart

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    I think you missed a "node point" in that circuit where the collector of Q5 connects to the base of Q7.

    Also you'll need to make the input voltage smaller to avoid any stages saturating. Are you able to make full transisent simulations showing actual voltage levels? You may have a significant DC offset in open-loop mode so you'll need to check for this by looking at actual voltage levels and not just AC values.
     
  13. Oct 4, 2009 #12
    i simulate it and get such value.29.16m/7.07u=4124,so the circuit is correct for gain 4000?how should i modify to get gain of 9000?
     

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  14. Oct 4, 2009 #13
    why i measure the v out is -1.2m while vx is 475 m.the v out not suppose to be larger than the vx?

    circuit source: Ron H from allaboutcircuits.com
     

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    Last edited: Oct 4, 2009
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