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Partial address decoder interfaced 68000-based system

  1. Nov 18, 2009 #1
    1. The problem statement, all variables and given/known data

    A circuit containing 24KB RAM is to be interfaced to a 68000-based system,so that the first address of RAM (the base address) is at $002000.
    (a)What is the entire range of RAM addresses?
    (b)Design a PARTIAL address decoder using three 8KB RAM ICs.

    2. The attempt at a solution

    for question (a) my answer is:
    The address range for the RAM is from $002000 to $002000+(24K=24*2^10=24576=$006000)=$008000-1=$007FFF

    Now I got problem for solving question (b).If I want to divide the address range ($002000 - $007FFF) into 3 (because of 3 8KB RAM), it will be
    ($002000-$003FFF) for RAM A
    ($004000-$005FFF) for RAM B
    ($00600 - $007FFF) for RAM C.
    Each one 8KB RAM has address A0-A12
    68000 does not contain A0 ,it only contain UDS*/LDS*.My question is, can I just interface address bus A1-A13 of 68000 to A0-A12 of RAM and not include UDS*/LDS*? .I 'm afraid it will be wrong because I have encountered example in the book which almost same with this question but it has 2 8KB RAM,it use UDS*/LDS* as chip select and lower byte will be in one RAM upper byte in another.
  2. jcsd
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