Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

PCB layout question

  1. Sep 25, 2012 #1
    I have 16 channels of the same circuit shown below.
    I have positive and negative power supplies ( 15V,-15V, 1A, TI LDOs).
    Can anybody tell me how to deal with power layout for the OP-AMPs if I use 4-layer (Signal-PWR_GND-Signal) PCB board?
    Please show me your picture if you have.
    Thank you!

    Attached Files:

    • 111.png
      File size:
      54.4 KB
  2. jcsd
  3. Sep 25, 2012 #2
    I don't know how critical is your circuit, I am just giving you the most stringent way good enough for low RF and no huge current surge which I don't see you have any high current surge circuit.

    1) put ground plane under components ( layer 2)so you have one continuous ground.

    2) Put power on layer 3. It is vitally important the spacing between layer 2 and 3 has to be very small. Make it 5mils. This will form a distribute capacitance between the power and ground and make the power plane an AC ground.

    3) Since you have to have cut on the power plane, put 0.01 cap from plane to ground at regular spacing along the cut. Make sure you put caps on both planes on each side of the cut and the caps are going in pairs on each side of the cut(one on each power plane). This will ensure the ground current has uninterrupted path so it does not have to go around to search for the return path.

    4) put 0.01 cap on the plane in the area with a lot of signal traces vias from top to bottom layer.

    With the caps pairs and close spacing power and ground plane, I literally mend the cut on the power plane and make it one complete plane through the distributed cap and the pairs of caps along the cut. How far apart each pair spacing along the cut depends on the highest frequency you are operating. If you are working into like 50MHz or higher, one pair every inch or so will be more than enough. The larger cap is not critical as long as you have enough.
    Last edited: Sep 25, 2012
  4. Sep 25, 2012 #3
    Thanks, yungman. Your reply are always so prompt and detailed.

    Sorry for the missing information. It's a low frequency case rather than a RF one. I put decoupling capacitances right next to each supply pin of OP AMPs.

    These OP-Amps uses dual supplies (+15 and -15 Volts with common analog ground). To make sure the power supply connection is short, should I put these negative power pins of OP-AMPs on the -15V power plane and the positive pins on the +15V power plane if I use Sig-GND-PWR-Sig PCB board?

    Thank you.
  5. Sep 25, 2012 #4

    His component selection suggests it's unlikely that the frequency of the application is high and the schematic suggests the physical size of the PCB will be small, so I'm not sure he'll see much benefit from tight coupling between the the gnd and power planes.

    In fact, I'd recommend doing the opposite: place the gnd plane (layer 2) close to layer 1 and, by symmetry, the power plane close to layer 4. This will reduce the signal loop areas and, as an added benefit, also reduce the required (microstrip) trace width if he's planning on controlling the trace impedance on those differential inputs. I'd then route anything critical on layer 1 and sleep well knowing that I had an uninterrupted low impedance return path in the solid gnd plane on layer 2.

    What do you think?
    Last edited: Sep 25, 2012
  6. Sep 25, 2012 #5

    I'm wondering if the responses so far (mine included) have been a bit overly enthusiastic. In an attempt to be more useful: yes, you connect the opamp +/-15V supply pins to the (split) power plane on layer 3. You have the right idea with the decoupling cap. And don't worry about the stackup, it will probably not be the defining factor of how well this circuit will work.
  7. Sep 25, 2012 #6
    gnurf, thank you.
    This forum is lovely coz a lot of ppl like u and yungman are here. :)

    Yes , actually I planned to place the GND (2nd) layer closer to 1st layer. Those critical signals will be placed on 1st layer.

    The component placement annoyed me much since there are so many of them. I guess I have to use wide power traces instead of split power planes on the PWR plane since there are 16 channels and I cannot place all the components into two split planes properly and compactly. Will that be ok?

    Another question is, the power distribution will be a multipoint type which is said to be a bad practice by some guidelines. I don't know how badly it will affect the circuit.
  8. Sep 25, 2012 #7
    Regardless of frequency, it is important to have power plane tightly couple within reason. You avoid a lot of noise problem doing that. Noise happen if the return ground current gets interrupted. Even at low frequency, the ground current ( called the image current) follow closely to signal forward current, if you have a signal trace on the bottom layer and cross between the two power plane, the ground current path got cut and has to find a round about way to complete the loop. Magnetic field form when a current form a loop, the bigger the loop, the stronger the magnetic field that can induce emf into other circuit. This is important and that's the reason boards don't pass emission test.

    Noise is not exactly a problem when the signals are running on the same layer without via to the bottom. It is always when the via that connects the signal from one layer to a different layer, then you really have to worry about the disruption of the image current. This board has 16 channel, it's going to be a sizable board.

    If you running a few KHz, then it is not important, but if you even running 100KHz, it is advisable to pay attention to this.

    But of cause, I am very conservative in pcb layout and I am known to overkill. So take this into consideration too.
    Last edited: Sep 25, 2012
  9. Sep 25, 2012 #8
    Using power trace is fine. In a certain way, it is better because you don't have a cut plane . Now you have only one ground plane, there should be no image current Make sure you have 0.1uF bypass cap very close to the power input of the opamp to the ground.

    What is a multi point distribution, I am not familiar with this name. Ideal is to have power input at one point, then star out and each trace goes to one section of the circuit, so you have 16. But in real world, it can be hard. I can't read the detail of the circuit, I don't know exactly what the circuit is doing, so it is hard to give detail advice. Do you have any high current device? Do you have any high speed device?
    Last edited: Sep 25, 2012
  10. Sep 26, 2012 #9
    I downloaded the schematic so I can enlarge it to see the detail, the image is still too blur to even see the part number of some. But I can see the opamp part the you are using 10M resistor on one and 190K as feedback resistor on the other.

    You have high gain in the circuit as you have one opamp running open loop and the second opamp has gain of 20 to form the closed loop feedback circuit AND the value of the resistance are too too high. 190K and 10K, that is gain of 20, you can use 19K and 1K. The higher the impedance of the opamp circuit, the more it is susceptible to emission noise.

    You have 16 channel, if you try to use power plane, the cutting is going to be very complicated and difficult. If you don't follow my precaution, you are going to create more noise. This compound with your high gain and high impedance circuit. Yes you are not running at any high frequency, but you have a lot of gain.

    My suggestion is, forget the cut power plane, you can make it worst. Star out power trace at one point and each go to one section. You might want to consider putting a small resistor in series from the power trace to the opamp and put 0.1 cap from the power pin of the opamp to ground. With high gain, you need to worry about cross talk on the power trace.

    I can't see the part number of the circuit on the right side, I don't know what it is so I can't even comment on that. Just the opamp on the left already bring your circuit into more critical category.
    Last edited: Sep 26, 2012
  11. Sep 26, 2012 #10
    At 5 mil (0.127 mm) seperation the inter-plane capacitance is about 30pF/cm^2. The effective interplane capacitance, however, is dependent on how fast a consuming IC needs charge. E.g., a digital circuit (which he doesn't have, but it serves well to illustrate the point I think) with a rise time of 1 ns would presumably need charge during that entire t=1ns interval, so all charge located further away from the IC than a radius of

    r = c*t = (0.3 m/ns) / √εr * t = 0.3 m / √εr = 14 cm

    would effectively be useless because it wouldn't reach the IC in time. In light of that I think my argument about small physical size is probably wrong.

    But let's say his PCB ends up being 10cm^2 and that all of this area makes an effective capacitor, then this would still only represent 3nF. This value is too small for effective low frequency decoupling, so typical 100nF caps must be used in any case, and so the 3nF is comparably small and insignificant.

    Therefor, for a low frequency four layer board, the small benefit you get by squeezing gnd and power (layer 3) together is by far outweighed by the upside of placing the gnd plane (layer 2) close to layer 1, mainly tight gnd-to-signal trace coupling (reduced gnd plane inductance, reduced crosstalk, etc) and reduced signal loop areas (reduced diff mode radiation, etc).

    Does that makes sense?

    I'd say crosstalk is a reason for tight coupling between signal layer 1 and gnd layer 2. The crosstalk between two signals is proportional to the square of their distance to the adjacent plane, so reducing the L1-L2 separation from 29mil* to 5mil would reduce crosstalk on a signal pair by 30dB.

    *1.6mm PCB = 63 mil, 5 mil L2-L3 seperation => L1-L2 and L3-L4 seperation = (63-5)/2 = 29 mil
    I decoded that to be an opamp (AD8227), can't you tell from the symbol in the schematics? ;)
  12. Sep 26, 2012 #11
    This is an important topics. Even slow frequency signal travel as EM wave, the current and voltage you measure ARE only the consequence of the boundary condition of the EM wave with the guided structure. You can really get into trouble if you put a cut power plane and not careful about it. In my first post, I did mention about putting 0.01 cap through out the surface of the power plane so even if the plane is not tightly coupled for low frequency signal, the image return path don't have to travel too far to find a path to the ground plane and reduce the area of the loop as much as possible. I work with signal integrity and this is a very important thing to know. Yes, at lower frequency, it is not nearly as important, but in circuit with high impedance and high gain, it is that much more sensitive to EM pickup. It is much better to use power trace than to have cut plane if you are not taking the precaution. Don't just cut the plane thinking it is better, it is not. This applies to low speed signals!!! It is very important to think EM in dealing with noise, not current and voltage. A power trace only cause very little disruption on the return path, unlike a big plane that is not properly coupled to the ground. 30mil separation between trace and ground is not that bad compare with 10 mil. We ran into problems during CE test that I traced down to one section that has a lot of cut planes, I did not even know better at the time. I only realize after I studied signal integrity and EM and realize how important it is. Same thing apply, don't cut analog and digital ground unless you really know what you are doing. This is playing with fire, one wrong cut, you'll be having problem. Use power trace in this case, you can't go wrong. Now you have 3 trace layers and the power trace can be in any of the three layers.

    Again, Yes, it is not as important when the frequency is low, but that does not mean not to pay attention to it as it is still more important than to have the ground layer closer to the top layer.

    I can see the opamp on the left side, I cannot see the curcuit on the right side that clear, I don't want to assume and this is not a circuit question, that's the reason I said I can't comment on that part. It sure don't look like opamp symbol and the circuit don't look like a simple opamp circuit.
    Last edited: Sep 26, 2012
  13. Sep 26, 2012 #12
    Also, there is one thing I forgot that is important enough to warren a new reply. The op already said he is going to forgo the power plane and use power trace instead. I think this is a much better and safer way. Don't put the ground close to the top.

    1) If the plane is farther from the center of the stack up, the board will warp. There is no way out of this. You design the stack up so the planes are symmetrical so there will be no net pulling to one direction.

    2) I would put as much signal trace at the bottom layer as possible because I don't even want the trace to have any interaction with the components on the top layer. I would not put most of the trace on the top layer. Let the ground plane insulate the trace from the components.

    I designed a lot of boards with very critical circuits and I layout most of my own board through out my career. I never ones see noise coupling because of the signal traces are not close enough to the ground plane yet. But I saw problem because of improper cut power plane, saddest part was to discover during the very expensive CE test.

    I just have few runs of small 3"X2" 2 layers board done, I have ground plane on one side, it sure warped. But I know before hand and it does not matter in my case.
    Last edited: Sep 26, 2012
  14. Sep 27, 2012 #13

    In an attempt to converge onto some common ground where we can (dis-)agree on specifics, I've quoted and paraphrased you on nine specific points which I hope we could deal with (some of them are unimportant).

    1) He has 16 channel of the same circuit, it is not going to be 10cm^2. It is going to be much bigger.
    I'm not sure why you think this is going to be such a large PCB, but you'll have to do a pretty bad job (size wise) to invalidate the point about the interplane capacitance being only a few nF and thus negligible at moderately low frequencies.

    2) Close coupling between the top signal layer and the adjacent ground plane is not important. It only affects the Z0 of the line. Signal-to-plane separation is only important when signals change layers.
    This is generally false. I've already mentioned crosstalk. Other benefits from tight coupling is reduced loop areas and hence differential-mode radiation, and also reduced ground plane inductance which reduces common-mode radiation from your cables.

    3) There's no radiation from microstrip because the EM wave is mostly contained in the guided structure. The only time there is an emission is when there is a disruption of the return path.

    4) If the signal trace doesn't go through layers, the only thing to worry about is the spread of current density on the ground plane.
    I'm suspecting my reading comprehension is letting me down, but I'm reading this as "No via = no EMI problems", which you probably don't mean.

    5) The only time noise coupling occurs is when you run a trace parallel along the signal trace.
    Which you will invariably do when you route sixteen channels on a PCB. This crosstalk depends on trace-to-trace and trace-to-plane separation, which is an argument for tight coupling between the trace layer and the adjacent plane layer.

    6) It is much better to use power trace than to have cut plane if you are not taking the precaution. Don't just cut the plane thinking it is better, it is not.

    Why is it much better? What's the difference? Doing the critical routing on L1 means that the split power plane on L3 is not a reference plane, and hence splitting the power plane on L3 is unproblematic.

    7) It sure don't look like opamp symbol and the circuit don't look like a simple opamp circuit.
    I was making a joke at the expense of whoever drew that symbol, and at the same time I was telling you that the device in question is AD8227.

    8) If the plane is farther from the center of the stack up, the board will warp. There is no way out of this. You design the stack up so the planes are symmetrical so there will be no net pulling to one direction.
    Warping has nothing to do with the L1-L2 separation because the solution is trivially, like you say and I did in my last post, a symmetric stackup.

    9) I would put as much signal trace at the bottom layer as possible because I don't even want the trace to have any interaction with the components on the top layer. I would not put most of the trace on the top layer. Let the ground plane insulate the trace from the components.
    This is horrible advice in my opinion. If you're worried about coupling between the top layer components and traces, then use guard fill gnd areas on that layer. Why introduce extra via pairs on all of your critical signals and route them on a layer that has no adjacent reference plane? Increased loop areas, etc..

    10) The op already said he is going to forgo the power plane and use power trace instead. I think this is a much better and safer way. Don't put the ground close to the top.
    What? No plane on L3, but you still don't want tight L1-L2 coupling?? That doesn't make sense.

    Ok, hope that covers it. I'm looking forward to your reply and maybe I'll learn something new! Cheers.
  15. Sep 27, 2012 #14
    I think you argue just for the sake of arguing? I usually don't engage argument in this forum. But you come out so strong and if I don't rebut you, people might think what you say is true!!! Have you study EMC layout and layout a board? Trace jumping through plane without taking into consideration of ground return image current is the single biggest reason of noise emission.

    On top of everything, we are not talking about having over 100mil spacing from top to the ground plane. I am talking about conventional 60mil boards that most people use. Even if you put the ground in the middle, it is only going to be 30 mils!!! This is NOT far in any respect for a lower frequency board. Again, you have to use common sense, this is answering to a general question. You want to argue and pick on every little point, the post will become a book on how to layout a pcb!!!!

    Of cause I know microstrip is not perfect structure and it does emit some noise, but it is not as critical as I explained above that the cross sectional area of microstrip is very small and it is normal to the board. I designed much more sensitive and high pulse current board and they were very high density. I never seen noise problem with same layer trace coupling problem. BUT of cause nobody in their right mind to intentionally run a sensitive trace in parallel for long distance to pickup noise just for the argument sake. You use common sense!!!

    At one time, one of my company called Optos hired a well known EMC specialist call Chris Kendell ( spelling? ) in the bay area to give a 2 days lecture on pcb layout, that ground image current and problem it can cause is the first, and the single most important part of his lecture. That's the reason there is a new category of engineer called signal integrity engineer in the pass 10 or so years specialized in this and I worked a bit in this.

    I shouldn't claim I know all the theory behind it as I studied the theory AFTER I know how to design pcb for ultra low signal environment. I did studied the noise coupling of microstrip and noise coupling in signal traces. I did spent a lot of time studying EM and EMC and so far, everything compliment each other. I spent over 20 years laying out pcb that is so much more sensitive than what the op posted to write my comments, and I stand by what I said.

    Remember, all the books on RF, microstrips etc. are a simplified way of explain the EM. It all boils down to magnetic field coupling:

    [tex]EMF=-\frac{d\Phi}{dt} \;\hbox { and } \Phi= \oint_s \vec B\cdot d\vec S[/tex]

    Look at the area enclosed by the microstrip and the direction that it is most sensitive. And yes, this is how loop antenna works. Another way to look at it is the return current follow the path of least impedance. For microstrip, the plane right under the trace will form a guided structure with the lowest characteristic impedance and that's where the return current flow. That's the reason why the image current follow very close to the top trace. This also will form a loop with the smallest area. Any break in the ground plane or interrupted by a cut power plane, the current has to find a round about path and form a loop with considerable bigger area. Even a 100K to 1MHz signal, the image current will follow closely below the top trace. Here is two articles look at page 20 to 21 of the first one:


    And page 21 of the following


    Are you using "Microstrip Lines and Slotlines by K.C Gupta and I.J Bahl?
    Last edited: Sep 28, 2012
  16. Sep 28, 2012 #15

    We are, and always have been, in complete agreement on the issue of discontinuities in the return path. I'm at loss as to why you keep harping on about that because the original argument I questioned was this one:
    I have argued for sig1-gnd2-pwr3-sig4 stackup with maximum separation between gnd (solid) and pwr, critical routing on sig1, minimal routing on sig4, and do whatever you want on pwr3 (split planes, thick traces, whatever) because it isn't a reference plane. If you object to this idea, then what are your reasons to do so and what is your better suggestion (in summary)?
    I'm not comparing the 2" by 30mil (0.06 sq in) loop area with a loop caused by a broken return path because the two are completely unrelated. What I am comparing it to is the smaller 2" by 5mil (0.01 sq in) loop that you'd get with 5 mil separation. The DM-mode radiation is proportional to the loop area and thus the DM-mode radiation caused by the bigger loop is 16dB greater than than of the small loop.

    As mentioned, the crosstalk between two traces is reduced by 30dB in the 5mil vs 30 mil case.

    I'm not that hot on magnetics, but it should be obvious that the mutual inductance between a trace and its return in a plane will maximized when the plane is close to the trace. This will minimize the return path impedance and the noise voltage that is developed across it. The latter is the big common-mode RF emission culprit, and as you might have noticed I have arrived at the same symptom as in the case of a slot in the reference plane (as discussed in the pdf you linked). But again, I'm not comparing the improvement of a 5mil layer separation to the effects of a slot in the ref plane, I'm comparing it to the 30 mil layer separation case.

    Considering that they come at no cost, that's three pretty good reasons I think for tight coupling between the signal layer and the ground plane. The only sacrifice you have to make is a few nF of distributed capacitance.
    Last edited: Sep 28, 2012
  17. Sep 28, 2012 #16
    Great discussion, guys, I'm saving this one to my reference archives, a LOT of useful guidelines in a very compact format. Yungman, keep cool, it's not personal, just a discussion, and I think there are some language issues as well so let's give the "benefit of the doubt" as to people's intentions and "tone". Gnurf, kudos for staying calm. The "heated debate" format is actually very productive as we (spectators) get the benefit of multiple viewpoints and multiple explanations of things rather than one guru dispensing wisdom in just one way. Thanks to both of you.
  18. Sep 28, 2012 #17
    As I said, unless people take precaution on split power plane, use power trace. Yes, you are right that a ground plane 5 mils spacing is better than 30mils, BUT, I am saying through experience that it is not a problem as long as you don't have split ground problem. Of cause, you exercise common sense not to run trace as close, bare in mind you have 30 mils separation. I don't have the number with me, but they do have guide lines on how far the adjacent trace has to be to be almost free of coupling( you never free of it). Yes, you have to put more distance between traces with 30mils than 5 mils, but that is a cheap price compare to split plane problem.

    And yes, if the plane is not in the middle, the board warp, the coef of expansion of copper and FR4 is not the same. There might be even other reason that I don't know. As I said, I have warping problem with my run of boards as small as 2"X3". It is not a problem if you know about it and it is ok with you. But if the board goes into a card slot or something critical, the warp can cost you a whole run.
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook