# Performance of the CPU

ciakamel
A micro-instruction sequencing and execution machine has a clock cycle
time of 10 ns and a base Cycle Per Instruction (CPI) of 5. The possibility
of interrupts and (or) exceptions may happen in the middle of an
instruction that must have copies of the values of the registers at the
beginning of the instruction. These registers are usually called shadow
registers. Assume that the average instruction has two register operands
that must be restored on an interrupt. The interrupt rate is 100 interrupts
per second, and the interrupt cost is 30 cycles plus the time to restore the
shadowed registers, each of which takes 10 cycles. Analyze the
followings:
i) What is the effective CPI after accounting for interrupts?

ii) What is the performance loss from interrupts?

iii) Is 10 cycles to restore shadowed registers realistic?

Anyone can help me with this question?

Mentor
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ciakamel
Welcome to Physics Forums!

Since you're new here, you probably haven't noticed the rules (see the Rules item in the menu across the top of the screen). Before we can help you, you need to have made an effort at solving your problem.

Ok,thank you, i will show my attempts.

siva_26
Same problem...can any1 help me 2 solve it????

siva_26
Bro can u help me too

Mentor
See what I said in post #2.

BTW, welcome to Physics Forums!

Mentor
Each instruction takes 5 cycles = 50 nsec, right?

Interrupt cost = 30 cycles + 20 cycles = 50 cycles $\neq$ 500 nsec.

Interrupts happen every 1/100 of a second, or every 10,000,000 nsec, meaning that an instruction won't get hit with more than one interrupt. This also gives you some idea of how often an instruction will get hit with an interrupt, which I think you need to take into account in the effective CPI.

ciakamel
Each instruction takes 5 cycles = 50 nsec, right?

Interrupt cost = 30 cycles + 20 cycles = 50 cycles $\neq$ 500 nsec.

Interrupts happen every 1/100 of a second, or every 10,000,000 nsec, meaning that an instruction won't get hit with more than one interrupt. This also gives you some idea of how often an instruction will get hit with an interrupt, which I think you need to take into account in the effective CPI.

got it, thanks for the help!