# Phase Locked Loop

## Main Question or Discussion Point

can the PLL achieve phase lock and not frequency lock?
and can the PLL achieve frequency lock and not phase lock?

Please advise. Thank You

## Answers and Replies

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Averagesupernova
Science Advisor
Gold Member
Isn't one completely dependent on the other? If you have 2 signals that are exactly the same frequency they may not be in phase but their phase relationship, whatever it may be, will remain constant.

In addition: as their operation relies on a phase comparator, they have to lock both the phase and the frequency.

Now, some PLL do offer the possibility to modulate the phase a bit and stay locked to the frequency (if all runs well).

Some PLL (the ones with a multiplier as a phase comparator) can also lock on an odd multiple or sub-multiple of the input frequency, without using an external divider. This operation is not very stable. Other PLL design want to preclude such modes, especially to lock over a wide frequency range, and have a sort of flip-flop as a phase comparator.

Phase locked loops are very interesting, although I had to read the section in Horowitz and Hill about ten times before I had the slightest idea what was going on.

Just as the name suggests, PLLs lock to a certain phase relationship with the input signal. Meaning that they don't lock to a frequency, they don't measure a frequency, they measure a phase difference (Phase Detector) and take a time average (Low Pass Filter). The result controls the output frequency (Voltage Controlled Oscillator). There is a pretty delicate balance required between the 3 components of a PLL for it to work as expected.

Consider a PLL used as a frequency multiplier. Say you have an input of 1 khz and you choose your VCO resistors and capacitor in such a way that a 0V signal into the input pin of the VCO gives 9khz and a +5V signal into the input pin gives 11khz. You choose a Low Pass Filter with a cutoff frequency at about 100-500Hz which will do your averaging, so any drift in your input frequency which takes place over a period longer than 2-10 milliseconds will be allowed to propagate through the filter and affect the VCO. Say you use type 1 phase detector, and you insert a divide by 10 counter between the VCO output and the feedback pin of the Phase detector.

To achieve lock, the output must be 10khz, which is halfway between the min and max frequency that the VCO has been configured to output. The voltage needed on the input of the VCO is halfway between 0V and 5V. How do you get 2.5V to appear on the output of the Low Pass Filter? Since the Type 1 Phase Detector is an XOR logic gate, its output is high when its two inputs are not the same, and low when its inputs are the same. For that output to be averaged to 2.5V, it must be high half the time and low half the time. Two square waves which are the same half the time and different half the time must be 90 degrees apart.

Simply speaking, it is impossible to be in frequency lock and not phase lock. Thats like having two parallel lines with different slopes. Frequency is the integral of the phase, the same way the equation of a line is the integral of the slope. Two parallel lines may be separated by a constant distance, and similarly two signals with the same frequency can be separated by a constant phase. In the example above, the constant phase difference is 90 degrees because thats what was required for the VCO to make the phase difference not change over time. If the resistors and capacitor were different, the VCO min and max would be different and the phase relationship would be different.

I have been wondering about a circuit that would attempt to lock to any frequency with an arbitrary final phase difference. I think I could do it by adding an analog subtractor in between the LPF and the VCO, but i haven't thought about it in a while. Can anyone make a suggestion on how to do this? Its for a resonant LRC oscillator which must be driven with a drive 90 degrees out of phase with the voltage across the cap in order to have Zero-Voltage Switching for max efficiency. Too bad NI Multisim doesn't have a good PLL simulator.

Averagesupernova
Science Advisor
Gold Member
What you describe should work within limits Greg-ulate. I've thought of doing this before.

NascentOxygen
Staff Emeritus
Science Advisor
I have been wondering about a circuit that would attempt to lock to any frequency with an arbitrary final phase difference.
To be able to select a phase difference anywhere between 0°...360° you'll need to make sure the phase detector is a type that works over that range. Some only operate 0°...180°.

But why design for arbitrary selectable phase difference, when you say that all you require is a 90° difference?

I think you are asking for two separate things. The whole principle of the PLL is that it's the phase difference between the VCO and the input signal that controls the VCO. So for any given PLL, this phase difference can be 90° only at one frequency.

It seems to me that, quite separate from locking to a shifting frequency, you need a circuit that gives a fixed 90° phase delay over a range of frequencies.

However, the application you then go on to cite seems not well represented by the above discussion.
Can anyone make a suggestion on how to do this? Its for a resonant LRC oscillator which must be driven with a drive 90 degrees out of phase with the voltage across the cap in order to have Zero-Voltage Switching for max efficiency. Too bad NI Multisim doesn't have a good PLL simulator.
Sure, you can use a PLL here. Just inject some DC into the VCO to offset the controlling voltage enough that the VCO settles down to a 90° difference at the frequency of operation. The LCR circuit won't be changing its frequency, so once it's locked the PLL does not find itself needing to chase a varying frequency.

Is this some sort of low frequency resonant circuit demonstration? You could wrap a few dozen turns of wire around one of the capacitor leads to sense the current it that wire and not use a PLL at all. Does any of the R in your design appear in series with the capacitor C? --because this current will be 90° ahead of the voltage.

It's all very well to go for zero voltage switching, but this point is where the current is a maximum, so expect sparks when you attempt to interrupt that current in the inductor.

Simply speaking, it is impossible to be in frequency lock and not phase lock. Thats like having two parallel lines with different slopes.
Not so fast. Suppose you have two parallel lines but one is a little squiggly. The average distance between the two lines is constant but not the distance between any two corresponding points.

The electronic equivalent is to try to frequency lock onto a RZ (Return to Zero) bit stream. The goal would be to recover the clock rate without the data. The average frequency of the bit stream is constant but not the instantaneous frequency. You'd never achieve phase lock but you could achieve frequency lock.

PLL can not achieve phase lock and not frequency lock
But PLL can achieve frequency lock and not phase lock.