Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

PIC uc latency time

  1. Dec 19, 2005 #1

    MSI

    User Avatar

    [​IMG]

    this graph shows a latency time diagram when an inturept request occure in a micro controller ..
    i was just wondering why doesnt the micro controller in the third machine cycle call the address "0004h" directly ?
    whats the use of this cycle ? ... still the micro controller can flush inst (PC+1) ,, while fetching 0004h in the next cycle ? :/
     
  2. jcsd
  3. Feb 1, 2006 #2
    Couple of possible reasons. First, many CPUs have a pipelines instruction. The instruction at PC + 1 is probably already decoded and execution may be difficult to stop and more effective to just let it complete. Second, the cpu may have to save some data before allowing the thread of excution to jump to another thread, such at status flags.

    To better answer he question would require significant knowledge of that particular processor.
     
  4. Feb 1, 2006 #3

    MSI

    User Avatar

    well the second is not possibel , because saving the registers is done through the intrupt, and the first one .. yea it do pipelining (: , but it is already shown in the figer .. and if pc+1 is a calling function .. there will be extra latency (not shown in the figure) ..

    anyway it is not a big deal (: , thanks
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?



Similar Discussions: PIC uc latency time
  1. Time Capsule (Replies: 0)

  2. Timing Circuit (Replies: 1)

  3. Import pics win7 (Replies: 4)

Loading...