can anybody help me with this question??? A 10 stage instruction pipeline runs at a clock rate of 1GHz. The data forwarding scheme and the instruction mix are such that for 15% of instructions one bubble, for 10% two bubbles, and for 5% four bubbles must be inserted in the pipelin. The equivalent single-cycle implementation would lead to a clock rate of 150 MHz. a. what is the reduction in pipeline throughput over the ideal pipeline as a result of bubbles? b. what is the speedup of the pipelined implementation over the single cycle implementation?? ANY HELP OR POINTERS WILL BE GREATLY APPRECIATED!!