PLA Circuit Confusion - Need Advice!

In summary, the conversation is about a student working on a PLA circuit for coursework and questioning whether or not to add extra connections to the AND and OR gates. The circuit has 7 incrementing values and 2 outputs. The student is concerned about the possibility of false outputs due to floating high and is seeking clarification on whether to connect the lines or leave them unconnected. The student also mentions not wanting to be accused of cheating and asks for advice on how to proceed.
  • #1
braceman
30
0
PLA.jpg
Hi all, quick question about a PLA circuit I'm doing for coursework. I'll upload a pic of the circuit to help explain. I've got the main stuff worked out but a little line in the coursework is making me think if I need to add a couple of extra connections on it. The circuit has 7 incrementing values and 2 outputs. Basically, my first output is going to be 0,0 and so I originally thought that I wouldn't need any connections to the AND gate or to the OR gates, however I noticed my notes saying that the AND gate would float high and give a false 1 o/p from it. Now if it was connected straight to a single OR gate this would give a false o/p but I have to connect the AND and OR gate lines myself (as there are 2 o/p's) . My question is this - if I leave the lines unconnected would the OR gate input float high too? My notes say that the 'product line' (AND gate I/p line) would go high but says nothing about the 'product term' (OR gate I/p line). My notes say that to get round this we just connect both outputs of the buffer that go to the AND gate.
Any ideas if I should just leave it in this situation or connect?

Edit - Sorry this isn't in the homework help format,,it's been moved by admin.
 
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  • #2
braceman said:
View attachment 84192 Hi all, quick question about a PLA circuit I'm doing for coursework. I'll upload a pic of the circuit to help explain. I've got the main stuff worked out but a little line in the coursework is making me think if I need to add a couple of extra connections on it. The circuit has 7 incrementing values and 2 outputs. Basically, my first output is going to be 0,0 and so I originally thought that I wouldn't need any connections to the AND gate or to the OR gates, however I noticed my notes saying that the AND gate would float high and give a false 1 o/p from it. Now if it was connected straight to a single OR gate this would give a false o/p but I have to connect the AND and OR gate lines myself (as there are 2 o/p's) . My question is this - if I leave the lines unconnected would the OR gate input float high too? My notes say that the 'product line' (AND gate I/p line) would go high but says nothing about the 'product term' (OR gate I/p line). My notes say that to get round this we just connect both outputs of the buffer that go to the AND gate.
Any ideas if I should just leave it in this situation or connect?

What device are you targeting? That diagram looks strange, with multiple connections fanning into single gates...

Can you post your work that led up to your PLA diagram? What is your State Diagram? What is your State Transition Table? What is the overall problem statement?

A more normal looking CPLD is like this:

http://www.seattlerobotics.org/encoder/200006/glb.gif
glb.gif
 
  • #3
It's just taking the inputs of a single bit full adder and putting in the connections to give the sum and carry outputs. I've taken some of the connections off as I've worked them out and don't want to be accused of cheating. All I need to know is if I need to put the extra connections to either the AND/OR lines or if it can be left as it is. There's nothing else on the question, they just gave the blank PLA diagram and what the O/P's should be.
 

1. What is PLA circuit confusion?

PLA circuit confusion refers to a situation where there is difficulty in understanding or interpreting the operation of a programmable logic array (PLA) circuit. PLAs are a type of digital logic device used in electronic circuits, and confusion can arise due to complex designs or errors in the circuit.

2. What causes PLA circuit confusion?

PLA circuit confusion can be caused by a variety of factors, such as errors in the circuit design, faulty components, or incorrect programming. It can also be a result of not fully understanding the operation of the PLA and how it interacts with other components in the circuit.

3. How can I troubleshoot PLA circuit confusion?

To troubleshoot PLA circuit confusion, it is important to first carefully review the circuit design and programming to check for any errors. Testing individual components and connections can also help identify any faulty components. Additionally, consulting with other experts or referencing technical resources can provide valuable insight and guidance.

4. Are there any common solutions for resolving PLA circuit confusion?

Yes, there are several common solutions for resolving PLA circuit confusion. These include double-checking the circuit design and programming for errors, replacing any faulty components, and seeking guidance from other experts or technical resources. In some cases, simplifying the circuit design or breaking it down into smaller sections can also help identify and resolve the confusion.

5. How can I prevent PLA circuit confusion in the future?

To prevent PLA circuit confusion in the future, it is important to carefully plan and design the circuit, thoroughly test and troubleshoot before implementation, and seek guidance from experts when needed. Keeping thorough documentation and records of the circuit design and any changes made can also help prevent confusion and aid in troubleshooting in the future.

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