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Homework Help: PLA question

  1. May 28, 2015 #1
    PLA.jpg Hi all, quick question about a PLA circuit I'm doing for coursework. I'll upload a pic of the circuit to help explain. I've got the main stuff worked out but a little line in the coursework is making me think if I need to add a couple of extra connections on it. The circuit has 7 incrementing values and 2 outputs. Basically, my first output is going to be 0,0 and so I originally thought that I wouldn't need any connections to the AND gate or to the OR gates, however I noticed my notes saying that the AND gate would float high and give a false 1 o/p from it. Now if it was connected straight to a single OR gate this would give a false o/p but I have to connect the AND and OR gate lines myself (as there are 2 o/p's) . My question is this - if I leave the lines unconnected would the OR gate input float high too? My notes say that the 'product line' (AND gate I/p line) would go high but says nothing about the 'product term' (OR gate I/p line). My notes say that to get round this we just connect both outputs of the buffer that go to the AND gate.
    Any ideas if I should just leave it in this situation or connect?

    Edit - Sorry this isn't in the homework help format,,it's been moved by admin.
    Last edited: May 28, 2015
  2. jcsd
  3. May 28, 2015 #2


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    Staff: Mentor

    What device are you targeting? That diagram looks strange, with multiple connections fanning into single gates...

    Can you post your work that led up to your PLA diagram? What is your State Diagram? What is your State Transition Table? What is the overall problem statement?

    A more normal looking CPLD is like this:

  4. May 28, 2015 #3
    It's just taking the inputs of a single bit full adder and putting in the connections to give the sum and carry outputs. I've taken some of the connections off as I've worked them out and don't want to be accused of cheating. All I need to know is if I need to put the extra connections to either the AND/OR lines or if it can be left as it is. There's nothing else on the question, they just gave the blank PLA diagram and what the O/P's should be.
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