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Please help me ly - D-Type Latch problem

  1. May 8, 2006 #1
    Please help me urgently - D-Type Latch problem

    Hi all,

    I have just descovered this wonderful forum and am hoping you can save my degree! I have to have this problem finished in a matter of hours and just can't figure out the schematics/truth tables. Please please please take the time to help in any way with any part if you can - it shouldn't be too hard for some of you experts and I would be eternally grateful. Thanks in advance,

    Oliver

    Here are the tasks:

    Design 1
    Design a 4-bit BCD counter that counts from 0 to 9. After 9 the counter should cycle through the same sequence again.

    Design 2
    Design a 4-bit binary counter which counts in binary from 0 to 15 then cycles through the same sequence again.

    Design 3
    Design a 4-bit BCD counter that has a direction input (which determines the direction of the count). If direction = 0 the counter should count down, alternatively if direction = 1 then the counter counts up. The input may change at any time and the count must change appropriately at the next clock edge.

    Design 4
    Design a 4-bit binary counter that has a direction input (which determines the direction of the count). If direction = 0 the counter should count down, alternatively if direction = 1 then the counter counts up. The input may change at any time and the count must change appropriately at the next clock edge.
     
  2. jcsd
  3. May 8, 2006 #2

    smn

    User Avatar

    Hi,

    Have you no ideas what so ever?

    Do you have to use d-types for the assignment?

    Are the counters synchronous or asynnchronous (do they need a clock input) ?

    Try researching D Type and JK counter circuits online, there's plenty of examples out there.
     
  4. May 8, 2006 #3
    Thanks for your reply, sorry, they are synchronous (do require a clock input) and all have to use D-Type latches, not JK flipflops. I have searched the net and come up with nothing which seems to help but this website. And no, I really don't know what to do - starting to get distraught about it all!

    O
     
  5. May 8, 2006 #4
    This is not that bad, follow the procedure in your book word for word.

    draw the state diagram, and use the excitation table for D latch to derive your equations.
     
  6. May 8, 2006 #5

    smn

    User Avatar

    For 1. - just think, you need to count from binary 0000 to 1001. After this count sequence the counter should reset. Couldn't the two outputs that are high (that represent decimal 9) be used to reset the count?
     
  7. May 8, 2006 #6
    Thank you for your reply, and I would imagine this is how one would do it however I am stuck as to how one would draw the circuit as a schematic as digital electronics is not my strongest subject! Would anyone be able to show me an example please?

    Thanks in advance.

    Oliver
     
  8. May 9, 2006 #7
    Right, managed to do design 1. Any ideas on the second?

    Thanks
     
  9. May 10, 2006 #8
    In the first counter you have to use four D- flip-flops which reset after 1001, that is as it reaches 1010 it is made into reset condition. For that you can pass the MSB flip-flop and 2 flip-flop output into a AND filter whose output is put into clear of all the flip-flops. In that way as the both the flip-flops output is 1 AND gate will pass 1 to clr of all flip-flops thus the counter is reset.
     
  10. May 10, 2006 #9
    For the second counter make a simple counter using 4 flip-flops without reset condition and yu get the counter that counts upto 15.
     
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