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Problem involving timing diagram with delays
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[QUOTE="Merlin3189, post: 6009398, member: 542077"] Interesting. I'd not come across this concept before (tcd.) I'll need to study it a bit to understand how it can be used. I'm not sure how you reach the 166 MHz. I can see this gives the time between pulses of 6 ns, which is tpd along the critical path. But I'm not sure why the circuit can't just output the 2 ns pulses with a delay of 6 ns (or more), until X is approaching 250 MHz. The start of the F pulse seems to follow the falling X and the end of the F pulse follows the falling X delayed by the inverter. This sets the F pulse duration at the propagation delay of the inverter - somewhere between tcd and tpd for that inverter. This pulse is delayed by the propagation delay of the OR gate. The limiting factor looks like having a second falling X before the Q has changed from the previous falling X - which will happen if Tx <= 2 ns, or Fx >=500 MHz. At 500 MHz, there is no F output. Upto 250 MHz the output pulses are 2 ns, but from there up to 500 MHz,the output pulses reduce in width, because they are terminated by the rising X after T/2 rather than the rising Q after the 2 ns tpd. In these diagrams, Q is the output of the inverter and F is a delayed copy of Q OR X. [ATTACH=full]226683[/ATTACH] [/QUOTE]
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Problem involving timing diagram with delays
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