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Homework Help: Program Trace [assembly]

  1. Nov 24, 2012 #1
    1. The problem statement, all variables and given/known data

    This question is being done using MARIE.

    Suppose initially AC = 1000, M[200] = FFFF, PC = 100. Trace the fetch execute (instruction) cycle of the following sequence of MARIE instructions using Register transfer notation (similar to Figure 4.14 of your text).

    Load 200 //PC = 100 here
    Add 200
    Jns 300

    3. The attempt at a solution

    I am using the same notation as my book.


    The problem is, in the textbook program the hex contents of memory is listed for 100,101,102... etc. In my program, i am only told that M[200] = FFFF. What happens when i try to access M[101]? Is it just zeroes? Am i right in assuming that?
  2. jcsd
  3. Nov 24, 2012 #2
    If you don't know what is there you cannot assume anything.

    But I think you do know what is there. Where is your program stored?
  4. Nov 24, 2012 #3
    Ohhh... I totally forgot that PC is 100 at the first instruction.

    So therefore, IR should be 3200 since Add is 3 and we're adding 200. Right?
  5. Nov 24, 2012 #4
    Adding the contents of address 200 to the accumulator, yes.

    You have the right idea; the opcode for Add is read from address 101. You'll have to trust yourself on the specifics since I don't know anything about Marie :)
  6. Nov 24, 2012 #5
    She is a cruel mistress.

    Okay so technically this program is loading FFFF then adding FFFF to it. Since MARIE uses 2's complement, this is the same (i think) as adding -1 to -1 which results in FFFD.
  7. Nov 24, 2012 #6

    -2 is FFFE

    +2 = ..0010
    complement = ..1101
    increment = ..1110 = E


    Whether the numbers are interpretted as unsigned or signed (2's complement), the result is the same. An unsigned addition FFFF+FFFF will also result in FFFE. Only the interpretation of the bits (by a human) will change.
  8. Nov 24, 2012 #7
    Oh my bad, that was supposed to read FFFE.

    Here's what i have.

  9. Nov 24, 2012 #8


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    Not included in your document is the description for JNS, but I found a document for MARIE computer doing a web search. JNS is a old style call instruction that stores the return at address X and then jumps to address X+1. On the JNS instruction, you left out the fetch (don't forget the PC = PC + 1 part), decode, and get operand descriptions. The opcode for JNS is 0000, but you left the IR as 3200, when it should be 0000 + address. The JNS "fetch" descritpion is really the "execute" description.

    Here's an extra question: After you've done the JNS 300, how could you use the JUMPI (jump indirect) instruction to "return" back to 103?
    Last edited: Nov 24, 2012
  10. Nov 24, 2012 #9


    On a related note, i have to decipher this program. Specifically, determine how many times the instruction at S is executed, and what is contained in Data when the program halts. I don't get how this can be determined since the input could alter how long it takes for the program to halt.

    Code (Text):

    000 5000 | S INPUT
    001 400A | SUBT Thirty
    002 300B | ADD Data
    003      | STORE Data
    004 100C | LOAD Round
    005 400D | SUBT One
    006 200C | STORE Round
    007      | SKIPCOND 400
    008 9000 | JUMP S
    009 7000 | HALT
    00A 0030 | Thirty DEC 48
    00B 0000 | Data DEC 0
    00C      | Round DEC 10
    00D 0001 | One DEC 1
    Last edited by a moderator: Apr 28, 2017
  11. Nov 24, 2012 #10


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    You have part of the JNS execute mixed with the decode. The decode for JNS is the same as the other instructions. The execute should include a M[MAR] = PC (103), or perhaps MBR = PC, then M[MAR] = PC (I don't know how this processor is supposed to work), followed by PC = AC.
  12. Nov 24, 2012 #11
    Our textbook shows the transfer notation for Jns as such:

    JNS X

    MBR <- PC
    MAR <- X
    M[MAR] <- MBR
    MBR <- X
    AC <- 1
    AC <- AC + MBR
    PC <- AC

    The only place where PC is used is at the very start and very end :S
  13. Nov 24, 2012 #12


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    The skipcond instruction is only affected by the last math operation, so the input does not effect the number of times the loop is run.

    This seems to be correct, but the fetch part of JNS is the same as it for all the other instructions. The fetch for JNS does not include MBR <- PC, that is part of the execute.
  14. Nov 24, 2012 #13
    I want to be doing MBR <- PC before PC <- AC in order to store 103, right? because otherwise 103 is erased.
  15. Nov 24, 2012 #14


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    MBR, PC, and AC are registers, memory is not erased when you do operations with the registers. The fetch for JNS and all instructions will be the same for this processor. Only the execute part will be different. Try writing the trace again for the JNS using the same fetch and decode as the other instructions, and then the execute as shown from your book.

    On side note, after doing the JNS 300, if the instruction at 301 was JUMPI 300, what would that do?
    Last edited: Nov 24, 2012
  16. Nov 25, 2012 #15
    Okay so if i'm understanding SKIPCOND right, it uses the second 2 digits of the operand to do its thing.

    So SKIPCOND 400 uses 00 which means that if AC < 0 it skips the next instruction. Which means that the instruction S will be executed twice since it's comparing the Round label to 0.

    I don't understand what it's asking me to say about the Data label when the program halts. Isn't Data dependent on the input?
  17. Nov 25, 2012 #16


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    It seems your book isn't explaining the instructions well. SKIPCOND uses the first 2 bits of the 12 bit operand, so 000 checks for AC < 0, 400 checks for AC == 0, and 800 checks for AC > 0.

    Again, could you try redoing the trace again for the JNS using the same fetch and decode as the other instructions, and then the execute as shown from your book. On side note, after doing the JNS 300, if the instruction at 301 was JUMPI 300, what would that do?
    Last edited: Nov 25, 2012
  18. Nov 25, 2012 #17
    I guess i'm confused why it uses 000, 400 and 800 to determine the action that SKIPCOND uses. It explains in the book that if IR[11-10] == 01 then it does an equality check, 00 is < and 10 is >. IR[11-10] in this case is 40 though, right? I thought we were working with individual bits and not hex....

    I find the mixture of binary and hex more messy than beneficial in this assignment. :/

    I'm not sure i follow what you want me to do with the JNS, It's basically the same as all the other instructions except at the execute stage it does things differently with the PC. I marked in green the 2 lines that might need to be moved around but the rest matches up with everything else.

  19. Nov 25, 2012 #18


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    It might be more messy, but you'll need to know how to code the SKIPCOND instruction using the conventional format, which uses hex, so if IR[11 10] = 00, then IR = 000, IR[11 10] = 01, then IR = 400, and IR[11 10] = 10, then IR = 800.

    You should not move those 2 lines around. The lines for fetch and decode should be identical to the lines you have for the other instructions. There is no get operand step, since memory is not being read. Your textbook doesn't explain that MAR will hold the value for X. See if you can complete the trace for JNS 300 starting with this partial trace:

    Code (Text):

    fetch           MAR <- PC
                    IR  <- M[MAR]
                    PC  <- PC + 1
    decode          MAR <- IR[11 0]
    execute         MBR <- PC
    In order to understand the purpose of the JNS 300, assume memory location 301 has a JUMPI 300 and do the trace for JUMPI 300.
  20. Nov 25, 2012 #19
    I think it's proper now.


    You'd just use the indirect jump on 300 since 103 is stored at that location.

    I have yet another question i can't solve.

    I'm supposed to be doing it using register transfer notation, but i don't know what value to use for the instruction. If i'm calling SDUP F01 then what would i put into the IR?

    This is messy and probably wrong but i dunno else what to do. Should i even be mentioning the AC in my solution?

    Last edited: Nov 25, 2012
  21. Nov 25, 2012 #20


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    If AC <- AC + MAR is allowed in addition to AC <- AC + MBR, then you wouldn't need to use MBR <- IR[11-0] again, but I don't know what is allowed on the processor. What you have now is correct.

    You'd be using SDUP FFF (instead of SDUP F01, M[FFF] contains the F01). You can make up any value you want, opcodes 0 through C are already used, so you could use opcode D, so the entire instruction for SDUP FFF could be hex DFFF. In this case, the fetch, decode, and get operand will be the same as your other instructions, since you need to get the stack address from memory at FFF. Try to create the trace using DFFF for the instruction word.
    Last edited: Nov 26, 2012
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