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Proteus: Creating a 16*8bit RAM with D flip flops

  1. Dec 30, 2013 #1
    1. The problem statement, all variables and given/known data
    Hey!
    I need to create a RAM in Proteus Suite. The RAM should have 16 storage spaces each containing 8bits of data (16*8bit RAM) and the output should be a three-state output. I've tried to create one, but I can't seem to get the hang of this three-state thing, and I think the even the decoders which I have used at the beginning of the circuit are not used in the right way as well.


    2. Relevant equations
    How should this be working? I get an error: Logic contention detected on net _______


    3. The attempt at a solution
    You can find it in the attachement below.
     

    Attached Files:

  2. jcsd
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