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Pspice and Ring Oscillator

  1. Mar 22, 2009 #1
    Design a digital ring oscillator using logic inverters that have propagation delay times of tPLH = 28ns and tPHL = 42ns.




    3. The attempt at a solution

    I'm using a general ring oscillator design using 3 CMOS inverters like this:

    http://upload.wikimedia.org/wikipedia/commons/7/75/Ring_osc_5.png

    I can't get this to work in Capture (Pspice) though. All I'm getting on the ouput is a DC signal. Can somebody explain to me how to get an oscillator to work in Capture? Also, how would you measure the tPLH and tPHL values?
     
  2. jcsd
  3. Mar 22, 2009 #2
    Sounds like you didn't set an initial condition for one of your gate voltages...
    I tried a simulation in both multisim and cadence orcad w/pspice.

    For OrCAD, choose the part "IC1" from the SPECIAL menu then enter an initial voltage (I used 0V).
    Connect this to any gate input of your inverters - then simulation should work.
    FWIW, I chose ON_MOS parts for simulation (MbreakN/P will not converge for simulation... at least for me)

    Same idea for Multisim, except you can add the initial conditions by editing the properties of the net.
     
  4. Mar 23, 2009 #3
    - I'm actually using an older version of Pspice Capture (v. 9.1 student edition) since it's free. So I made my logic inverters with the EVAL parts IRF150 and IRF9140. I tried adding the IC1 part to the gate and it would only give me the first rise and then it would stay high endlessly. Is there maybe something wrong with using those MOSFETS?
     
  5. Mar 23, 2009 #4
    Could you post a screenshot / printout of your OrCAD schematic? I found your IRF150 under PWRMOS and the simulation worked fine for me.

    One thing to note, are you sure your pmos bulk is correctly connected to vdd? For me, the part initially is 'upside down' according to how I usually layout my digital transistor schematics; and my first mistake was not noticing this - had to mirror the pmos vertically to correct this issue. This misalignment produces a simulation result similar to what you mention...

    If that doesn't help I'll be glad to post my schematic/plots.
     
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