Based on a circuit diagram below
The Attempt at a Solution
So I was going through some past exams papers and encountered this question.
However at the top it says it's a Pull-down circuit.
Now I know that pull-down circuits utilize nmos transistors and pull-up circuits utilize pmos transistors, so the diagram coincides with that convention.
However the circuit is established between Vdd and the output...so it's setup as a pull-up circuit(atleast to me). So if it's a pull-up circuit then the soln would be basically to convert that diagram to Boolean form.
But if it is in fact pull-down circuit then the soln would be the dual of the above.
Which should I take it as in order to work out the soln.
Thanks in advance.