How do you decide the value of the resistor?

[likephysics]

Dumb question.
Can't seem to understand how pull up resistor works when interfacing TTL to CMOS.

A TTL output connected to a CMOS input.
TTL output is 3.3V, but CMOS requires 5V.

When TTL output is high, one end of resistor is 3.3V and the other end is 5V.
The 3.3V end is connected to cmos input. How does the cmos input see 5V?
ckt diagram here -http://www.ecelab.com/interfacing-ttl-cmos.htm

Also, how do you decide the value of the resistor?

 

[mheslep]

Dumb question.
Can't seem to understand how pull up resistor works when interfacing TTL to CMOS.

A TTL output connected to a CMOS input.
TTL output is 3.3V, but CMOS requires 5V.

When TTL output is high, one end of resistor is 3.3V and the other end is 5V.
The 3.3V end is connected to cmos input. How does the cmos input see 5V?
ckt diagram here -http://www.ecelab.com/interfacing-ttl-cmos.htm

Also, how do you decide the value of the resistor?

The examples in your link show open collector TTL, so that the output is not 3.3V, but either 'open' or closed. That is, when the output transistor is off the collector is at high resistance, or 'open', relative to the pull up resistor only the micro amp collector leakage current flows so that their is little or no drop through the pull up and the collector voltage is nearly the same as the supply voltage Vcc, which is sufficient to drive the input of the high input resistance CMOS gate. When the output transistor is biased on, the collector voltage is forced to Vce-on (~.2-.3 V) above ground. Then the trade off for selecting Rpull-up is that it should be very small compared to the transistor off resistance, but the smaller the resistor the more power it wastes in heat. With a 5V supply a 1k ohm resistor would burn ~25mW.

 

[likephysics]

The examples in your link show open collector TTL, so that the output is not 3.3V, but either 'open' or closed. That is, when the output transistor is off the collector is at high resistance, or 'open', relative to the pull up resistor only the micro amp collector leakage current flows so that their is little or no drop through the pull up and the collector voltage is nearly the same as the supply voltage Vcc, which is sufficient to drive the input of the high input resistance CMOS gate. When the output transistor is biased on, the collector voltage is forced to Vce-on (~.2-.3 V) above ground. Then the trade off for selecting Rpull-up is that it should be very small compared to the transistor off resistance, but the smaller the resistor the more power it wastes in heat. With a 5V supply a 1k ohm resistor would burn ~25mW.

I understand the open collector pull up. But can you explain how it works when there is an external pullup resistor(like in fig1 in the link)?

 

[Bob S]

Fig. 1 is a totem pole output. You should use the open collector output if avail because you get a higher level "1" voltage.. They show 10k resistor pullup, but I usually use about 2k (2.5 milliamps w/ collector low)

 

[vk6kro]

CMOS require less than 1.5 volts for a zero and more than 3.5 volts for a one.
TTL can't do this reliably (unless you use open collector gates) so you usually need to put an interfacing transistor into be switched by the TTL and give a reliable 0 to 5 volts out.

Putting a transistor in introduces an inversion though, so it may not suit the logic.

Fortunately TTL are not used much any more. The 74HC family are very nice to work with and use a fraction of the power that the old TTL monsters used to use.

 

[berkeman]

Dumb question.
Can't seem to understand how pull up resistor works when interfacing TTL to CMOS.

A TTL output connected to a CMOS input.
TTL output is 3.3V, but CMOS requires 5V.

When TTL output is high, one end of resistor is 3.3V and the other end is 5V.
The 3.3V end is connected to cmos input. How does the cmos input see 5V?
ckt diagram here -http://www.ecelab.com/interfacing-ttl-cmos.htm

Also, how do you decide the value of the resistor?

Not a dumb question at all. That link provides very poor information, so it's no wonder you are confused. If you drew that top circuit in response to my interview question about how to interface the different logic families, it would be a short interview.

Those are not real-world techniques for interfacing logic families. Quiz Question -- why? (not a QQ for the experienced folks here, let the students answer it...). Hint, how would you calculate the max signal BW that could be propagated across that boundary?

If you have a TTL signal (or a 3.3V CMOS signal) that needs to cross into 5V CMOS logic, you use ACT or HCT or some other XXT logic gate to do the job. QQ -- what does the "T" stand for in those logic family variants?

Or you use some other *active* level translator gate. There are even very cool bidir level translators that you can use on bidirectional busses with different voltage devices all sharing the same bus.

 

[bitrex]

Those are not real-world techniques for interfacing logic families. Quiz Question -- why? (not a QQ for the experienced folks here, let the students answer it...). Hint, how would you calculate the max signal BW that could be propagated across that boundary?

I had to think this over while having lunch so I'll take a stab at it - my guess is that the reason the pullup resistors would not be a good solution at high signal frequencies is that there's an input capacitance on the gate of the next IC, and when the open collector output transistor shuts off and the output goes high the capacitance of the next stage has to charge up through that pullup resistor, introducing a nasty time constant and distorting the signal. :yuck:

 

[mheslep]

I had to think this over while having lunch so I'll take a stab at it - my guess is that the reason the pullup resistors would not be a good solution at high signal frequencies is that there's an input capacitance on the gate of the next IC, and when the open collector output transistor shuts off and the output goes high the capacitance of the next stage has to charge up through that pullup resistor, introducing a nasty time constant and distorting the signal. :yuck:

That is exactly the problem. Sorry I should have mentioned this previously.

 

[likephysics]

I guess no body really answered the question. Connecting a pullup is similar to connecting 2 resistors to the collector of a transistor. one is internal and the other connected to +5V, right?
Can somebody point me to a link where I can see the output stage of a TTL gate. I don't know why the output(Voh) is 3.3V
I am guessing the output stage is just like a NPN switch.

 

[dlgoff]

I like this Fairchild application pdf for http://www.fairchildsemi.com/an/AN/AN-314.pdf" . Just thought I would share.