Question in symbolism

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Question in symbolism....

[IMG=http://img43.imageshack.us/img43/1997/symbolx.png][/PLAIN]

I was looking at a book with the same symbolism as above on the left and i assumed that the bulk was always connected to the source.Yet at some point i saw this....

http://img707.imageshack.us/img707/8231/whyj.png [Broken]

Why the difference here?if the default in the symbolism is for the bulk to be connected to the source why is there a difference here?
 
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  • #2
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[IMG=http://img43.imageshack.us/img43/1997/symbolx.png][/PLAIN]

I was looking at a book with the same symbolism as above on the left and i assumed that the bulk was always connected to the source.Yet at some point i saw this....

http://img707.imageshack.us/img707/8231/whyj.png [Broken]

Why the difference here?if the default in the symbolism is for the bulk to be connected to the source why is there a difference here?
You can see it below (a NAND gate) - your example is a NOR gate but it's the same thing - a NOR would do what I'm describing for NAND but on the PMOS transistors instead (like your circuit):

There is little layout trick often used in MOS design: implementing series transistors without popping back up to a metal layer. It saves space and is two less contact failure points.

You see this in the NMOS devices (bottom) where the series NMOS transistors are implemented as shown. The green is source-drain implant mask. The red is poly mask for the gate and define the self-aligned source-drain channel boundaries.

Compare this to the parallel PMOS devices on top. Notice that the source of the top NMOS transistor is the drain of the bottom NMOS transistor. The implant for that source-drain node (imagine the rectangle defined by the edges of poly and implant) is floating, ergo, not connected to the substrate or floating like the circuit symbol. Seeing this in the schematic tells you that this layout technique was used.


[PLAIN]http://www1bpt.bridgeport.edu/~matanya/images/ict2.gif [Broken]
 
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Thanks for the reply.This is actually part of an analog circuit.So to simulate the general behavior o the circuit in a typical schematic cad tool how do I handle this one?
 
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The simplest answer is the typical SPICE way: either leave the terminal unconnected if the model allows it or put a large resistor from the node to source or macromodel as a resistor and reverse biased diode.
 

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