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Read Only Memory (ROM)

  1. Nov 22, 2016 #1
    1. The problem statement, all variables and given/known data
    We have been introducted to ROMs in class. I just have a few questions to make sure I'm getting this concept correctly.

    44fc8831b5.jpg

    The intersection between the lines are called crosspoints. At each crosspoint there are programmable fuses. The fuses can either be unchanged(short circuit) meaning that the crosspoint would be connected the two wires. Or the fuse can be blown(open circuit) meaning that the crosspoint would no longer be connecting the two wires. Connected cross points are repersented by an x.

    Q1 ) Is my understanding correct?

    Q2) if I see an X on a diagram like the one above, that means that it is an untouched fuse which is making a short circuit right?

    Q3) Take the first line in the diagram above(decoder output 0.) In my notes, my lecturer has the corresponding 'word' or 8 bit/1 byte binary code for output 0 as : 10110110. He is taking each X(connected cross point) as a 1. Why? How do connecting cross points automatically become a 1?

    2. Relevant equations


    3. The attempt at a solution
     
  2. jcsd
  3. Nov 22, 2016 #2

    berkeman

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    Sorry, that makes no sense to me at all. Can you link to the original content?
     
  4. Nov 23, 2016 #3
  5. Nov 23, 2016 #4
    The first line of the truth table(00000 inputs) corresponds to the first horizontal line in the diagram(decoder output 0.) If you note every time there is a X on the horizontal line, the corresponding bit has a 1 in the truth table. Why is this?
     
  6. Nov 23, 2016 #5

    Merlin3189

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    For your main question, Q3, I'll leave it to CoolDude for now, as he's started on one tack.
    For Q1, I think your explanation is more or less ok, depending on how full an understanding you want. (See Q2)
    For Q2, If they really were short circuits at the marked cross points, when you had a 1 on, say, decoder output 3, which of the A's would be connected by shorts to that 1 signal? (If you don't get a flash of enlightenment when you first think about it, try tracing the route of the electric current from the 31 line to each of the A's.)

    Edit: changed Berkeman to CoolDude as I'd put the wrong name.
     
    Last edited: Nov 23, 2016
  7. Nov 23, 2016 #6

    gneill

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    The trick is to note that each of the OR gates actually has 32 inputs (slide #32). So the vertical line with the X's that extends from the matrix to the OR gate is actually a 32 bit wide bus. The X's represent where the bus taps onto the corresponding horizontal lines. So the first OR gate, if if you were to look at the "expanded" view would look something like:
    upload_2016-11-23_9-29-41.png
    where I've used dots rather than X's for the connections.
     
  8. Nov 23, 2016 #7

    rcgldr

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    Technically this is a one time (there's no way to undo disconnections made by blowing fuses) programmable rom (PROM) . Normally a ROM is manufactured with a circuit that only includes the connected lines. For Q3, although not shown, there's a voltage input line (a 1) on the 5 x 32 decoder, so if all 5 inputs bits are zero, it outputs a 1 on output pin 0, and a 0 on all of the other output pins.
     
  9. Nov 23, 2016 #8

    Merlin3189

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    Maybe I misread the earlier posts, so I'll tackle Q3 as well.
    When he says, "decoder ouput 0" in the first line of the ROM, he means, "the decoder output labelled "0" becomes true, or takes the voltage level for a logic 1, when the decoder input is 0000." Similarly the next line is "decoder output 2" which becomes logic 1 voltage when the input to the decoder is 00010. And so on down to "decoder output 31 which becomes logic 1 voltage when the input is 11111".
    It doesn't matter whether the decoder inputs are all 0's or all 1's or any mixture. All the decoder outputs will be set to 0, except for exactly one of them, which will be set to 1. The decoder logic simply decides which one it should be, depending on its inputs. Decoders normally generate the inverse of all their inputs (so that input 00000 generates 11111 say) then use AND gates to combine them. Eg. output 23 is the AND of I0, I1, I2, I4 and inverted I3. This makes it a 1 for input 10111 and 0 for all other inputs.

    Crosspoints become 1 when the decoder output connected to them becomes 1. So when you input 00000, decoder output 0 becomes 1 (the rest, 1-31 become 0) and output lines 7,5,4,2 and 1 become 1 via the cross points (the other outputs 6,3 and 0 remain at 0.)
     
  10. Nov 23, 2016 #9

    Merlin3189

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    I hesitate to tangle with a Mentor in his specialist area, but I believe gneill is either mistaken or being a bit disingenuous with his description of the ROM array using 32 input OR gates.. If you answer my supplementary to Q2, you may see a sense in which his idea represents the logic of what is being done, but I'm pretty sure that ROMs were not implemented that way, at least in TTL. (I'm much less familiar with later families.) I certainly have 256 byte ROM from the 1960's where I know the full circuit, in which the circuit is pretty much as shown in the first diagram, except for; an 8 bit decoder, pull-up resistors, the buffers are inverters and the vital detail missing from Q2.
     
  11. Nov 23, 2016 #10

    gneill

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    Just using the given information:
    upload_2016-11-23_14-7-0.png
     
  12. Nov 23, 2016 #11

    Merlin3189

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    Apologies gneill. Yes, I missed that bit of the post. I should know from past experience that you guys are pretty sharp and not usually mistaken.

    I don't know now whether Hector Allford is using these OR gates symbolically or whether they really do make them like this. The one I knew certainly had an array of diodes shown in the schematic , but in IC fabrication this is so close to multiple emitter transistors, that perhaps they are generally implemented that way?
    Perhaps my schematic, and functional diagrams like PROM _Eg.jpg , are in fact the myth to aid electricians' understanding and your diagram is the silicon reality? The logic works the same either way.

    Slide 33 in the OP, which I thought missed the essential detail of the crosspoints, is probably just intended just to show the logical relation between the decoder lines and the outputs.
     
  13. Nov 23, 2016 #12

    gneill

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    It is quite likely that the OR gate representation is symbolic in that it describes the logic that's implemented without specifying the physical details of that implementation. A diode array can certainly be the underlying circuitry (So, diode logic implementation of the OR function) at least for some early ROM devices. In practical terms the diodes prevent the decoder outputs from affecting each other.
     
  14. Dec 15, 2016 #13
    Apologies for the late reply. Have been really busy with other modules. I finally think I understand what's going. Realising that theres 32 inputs to each OR gate makes everything much clearer. Thanks for the help all.
     
  15. Dec 18, 2016 #14

    CWatters

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