1. The problem statement, all variables and given/known data The question states that when S = R = 1 and clock = 1, both outputs are 1. When clock goes to zero, Q becomes 1 and ~Q becomes zero. But if two NAND gate inverters are placed between ~Q and the input of gate 3, when clock goes to zero, Q becomes zero and ~Q becomes 1. The question asks to account for that, they also say that assume gates 1 and 4 switch faster than gates 2 and 3. 2. The attempt at a solution First I thought that the propagation delay of the two extra inverters would cause that but as they specifically say that gates 1 and 4 are faster than 2 and 3, the speed of the two branches should be equal with the extra gates. Does the question have to do anything with the fact that operation is unpredictable when both S and R = 1? Or is it the propagation delay?