# S-R bistable question

1. Jan 25, 2016

### bizuputyi

1. The problem statement, all variables and given/known data

The question states that when S = R = 1 and clock = 1, both outputs are 1. When clock goes to zero, Q becomes 1 and ~Q becomes zero. But if two NAND gate inverters are placed between ~Q and the input of gate 3, when clock goes to zero, Q becomes zero and ~Q becomes 1. The question asks to account for that, they also say that assume gates 1 and 4 switch faster than gates 2 and 3.

2. The attempt at a solution

First I thought that the propagation delay of the two extra inverters would cause that but as they specifically say that gates 1 and 4 are faster than 2 and 3, the speed of the two branches should be equal with the extra gates. Does the question have to do anything with the fact that operation is unpredictable when both S and R = 1? Or is it the propagation delay?

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2. Jan 25, 2016

### cnh1995

I believe it is happening because of the propagation delay of the two extra inverters. If you examine how the input propagates to each gate, you'll see the inverters' delay is responsible for the second case. Q- becomes 0 early, but due to propagation delay of the inverters, it becomes 1 before feeding the earlier 0 to gate 3. What exactly is the queation here?

3. Jan 25, 2016

### bizuputyi

They ask to explain with the two inverters inserted in why Q becomes zero and ~Q becomes 1 when the clock reverts to zero. So, again without the two inverters when clock reverts to zero, Q becomes 1 and ~Q becomes zero and with the inverters in this is the other way round. Why is this the case?
I believe its the propagation delay but not sure how to put it into words exactly.

4. Jan 25, 2016

### cnh1995

Consider the second case. Q and Q- are initially 1. When CLK=0, output of gate 1 is 1, hence, inputs to gate 4 are now 1 and 1 which yields Q-=0. Due to delay of two nand gates, this 0 will not be fed to gate 3 immediately. Meanwhile, inputs to gate 3 will still be 1 and 1 and hence, Q will be 0. Q=0 will force Q- to become 1. So, Q- initially becomes 0 but can't feed it to gate 3 and by the time the 0 passes through two inverters, Q becomes 1 and forces Q- to become 0. Two nand gates should have more delay than the delay of gates 2 and 3.

Last edited: Jan 25, 2016
5. Jan 25, 2016

### bizuputyi

That makes sense to me nicely. They specifically say that gate 1 and 4 switch faster than 2 and 3. If just assuming that switching time of 1 and 4 plus the two inverters equal to the time of 2 and 3, which case would happen when the clock goes to zero?

6. Jan 25, 2016

### cnh1995

This means delay of two nand gates is less than the delay of 2 and 3.
Take delay of 1,4 and the two nand gates to be 1nS and that of 2 and 3 to be 2 nS. Initially, S=R=Clk=Q=Q-=1. When CLK becomes 0, the inputs will propagate at different speeds and will generate a square wave at the outputs.Hence, in this case, it will be an astable multivibrator.

Last edited: Jan 25, 2016
7. Jan 25, 2016

### bizuputyi

Ok, I see. In that case we don't assume that time delay 1,4 + time delay two NANDs = time delay 2,4.
Also to achieve Q = 0 and ~Q = 1 with clock falling to zero the delay of the two NANDs must be less than gate 2 and 3. And delay of 1,4 + NANDs > 2,3. Is that right?

8. Jan 25, 2016

### cnh1995

.
When we took delays as 1nS and 2 nS in previous examples, it was for the case
delay 1,4+ delay two nands=time delay of 2, 3.
I haven't verified it but sounds correct to me. You can do it by taking suitable delay values.

Last edited: Jan 26, 2016