Sequential Logic Design--State Diagram for a divider I need to design a divider so that when input C=0 it divides by 3 and when input C=1 it divides by 4 and I need to use D,T,and JK flip flops (I'm not even sure I'm phrasing this correctly). I'm just having trouble with a few concepts. I'm trying to figure out the state diagram my professor gave us and then I think I might be able to figure out how to do the design(hints are welcome though). State diagram is below(I couldn't get the image to imbed): http://imgur.com/9mr4B If I think I understand this correctly it looks like a counter and the input C is a 'don't care' for the first two counts, then it stops at 2 if C is 0 or stops at 3 if C is 1. I'm not sure about this at all though. What are the numbers on the bottom inside of the bubbles? He also mentioned something about Nclk (new clock maybe?) which I don't understand at all (he never explained it). I have to include it when I do the timing diagram. Is it the clock going from one flip flop into another or something like that? Here is the picture I had in my notes, probably doesn't help though: http://imgur.com/U8ub5 Thank you in advance for your help and time. If you could briefly explain the general concept of a divider it would help too.