Why Does Increasing Sampling Frequency Fix Sequential Logic Simulation Issues?

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[SOLVED] Sequential logic simulation

I have built a circuit (using the SystemVue software package) that has a 5 bit adder (adds two 2s-complement five-bit numbers - A4A3A2A1A0 and B4B3B2B1B0) with overflow detection and saturation circuits. I am trying to clock the data in so I can check if it works with all possible combinations of the two input numbers. Hence I have 10 JK flipflops cascaded at the input as a frequency divider (all Js and Ks tied to 1, Q fed into clock of the next flipflop). Therefore I get all possible combinations of A's against every possible combination of B's for the input carry being both 0 and 1.

All of that seems more or less fine to me. What is causing me problems is simulating this circuit. I am feeding a pulse train into the first flipflop with a frequency of 1024 Hz and a pulse width of 50e-6 s. I then set the simulation to run with 1024 samples with a sampling frequency of 4096 Hz. The estimated time is determined (by the system) to be 0.4 s. It actually takes about 4 minutes to do the simulation. And if I set up a probe at the pulse train source, it gives a straight line, no sign of a pulse train. I think what I am having trouble with has to be something to do with the sampling rates and simulation. I don't understand it that well and have introductory DSP only next semester.

Does anyone have any idea why the output of the pulse train is staying constant and what I might be doing wrong?

EDIT: Hmm, choosing a sampling frequency at least 4 times the number of samples (say 256 samples, then at least 1024 Hz sampling frequency) made it work. I don't know why, but it works now.

 

[KataKoniK]

Hello,

Thank you for sharing your circuit and simulation setup. It sounds like you have a good understanding of the circuit and its components. From your description, it seems like the issue may be related to the sampling frequency and number of samples used in the simulation.

In general, when simulating sequential logic circuits, it is important to choose a sampling frequency that is at least four times the highest frequency component in the circuit. This is known as the Nyquist-Shannon sampling theorem. In your case, it seems like your pulse train has a frequency of 1024 Hz, so choosing a sampling frequency of at least 4096 Hz is a good choice.

Additionally, the number of samples used in the simulation should also be considered. As a rule of thumb, the number of samples should be at least four times the number of clock cycles in the circuit. In your case, since you have 10 JK flip-flops cascaded, the number of clock cycles would be 10. So, using 40 or more samples in the simulation would be a good starting point.

I hope this helps to explain why increasing the sampling frequency and number of samples has resolved your issue. If you have any further questions or need more clarification, please feel free to ask. Best of luck with your simulation!