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Silicon binning techniques

  1. Aug 11, 2008 #1
    Hi all.

    A little while ago I overheard my cousin chatting with a friend who works in the semicon industry about the binning process. He was specifically talking about MPU binning techniques in use nowadays and I overheard him mention something to the sound of "boutique line binning". :confused:

    I have no idea what it is, but I only remember scant notes of what he mentioned - something to do with pushing some sort of line (L gate?) further to produce higher FMax bin silicon at the cost of power and expense (usually the expensive models/power consuming by any MPU MFG).

    I've searched online and not found reference to this anywhere. Can someone explain to me what this is and provide a reference to study about it?

    Also how is it possible to distinguish if this technique is being used on a CPU, after production by an individual? Are there telltale signs?

    Thanks for the help.
     
  2. jcsd
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