1. Not finding help here? Sign up for a free 30min tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Simple Circuits (Electricity)

  1. Nov 25, 2014 #1
    1. The problem statement, all variables and given/known data

    2ptt24l.jpg

    2. Relevant equations

    ##v1 + v2 + v3 = 0## (KCL)

    3. The attempt at a solution

    20gjj8w.jpg

    I don't understand why my solution is wrong. I was taught that if I were to use Node Voltage analysis, I should put nodes with voltage sources into supernodes which was what I did, however, my teacher showed a rough guide in class and he did not use supernode.

    Hence, I am a bit confused now -- when do we use supernodes and if we use supernodes, how big should they be? For the question above, if I were to use supernode, assuming I made some calculation errors above, will I get the same answer as my teacher? Thanks!

    My teacher's partial solution:

    123qhop.png
     
  2. jcsd
  3. Nov 25, 2014 #2

    gneill

    User Avatar

    Staff: Mentor

    A Supernode in this case would include the reference node and the source 2v. It does not include R4. But you don't need to write an equation for the reference node, just the two other nodes, v and v2.
     
  4. Nov 25, 2014 #3
    What do you mean by the reference node? Does it mean that I must not cover the resistor R4?

    [/QUOTE]But you don't need to write an equation for the reference node, just the two other nodes, v and v2.[/QUOTE]

    I see. Hmm.. Then when we do know when not to use supernode? This is because, I usually would put voltage sources in supernodes whenever I see them in a circuit.. May I know if this is bad practice/a misconception? :(

    Thanks! :D
     
  5. Nov 25, 2014 #4

    gneill

    User Avatar

    Staff: Mentor

    First you select a reference node. In this circuit the bottom rail is the natural choice.

    Any sources directly connected to the reference node are effectively part of a supernode. But you don't need to write a node equation for the reference node since by definition it has the known potential 0V.

    In other locations a supernode comprises a set of nodes whose potentials with respect to each other are fixed by voltage sources and thus independent of any current flowing between them. A resistor in series with a voltage source doesn't work because a change in current changes the potential across the resistor, thus altering the end-to-end potential difference of the combination.
     
  6. Nov 25, 2014 #5
    I see. OH YA! Sorry about the issue on reference node. I had always called it the "ground -ve 0" node because I always fix it, usually on the negative end of independent voltage sources, and where the end lands on the other nodes with nothing in between the nodes so I can put 0V across left to right and vice versa, so the term reference node slipped my mind. ><

    Ah yes. My teacher said that supernodes can be of any size, since a supernode is a collection of nodes.

    I see. So that means I cannot put a supernode at the dependent voltage source, because I will not be able to loop it after and around R4, which makes it look funny, and hence I should not do it. Am I right to say this? I attempted to draw a supernode below, according to what you have said above, to be sure I did not interpret your message wrongly. :)

    2gwrkvo.png
     
  7. Nov 25, 2014 #6

    gneill

    User Avatar

    Staff: Mentor

    The reference node and the directly attached sources can be considered a supernode.

    Fig1.gif

    The potential at the top of v1 is, well, v1. And the potential at the top of the 2v source is 2v. These are fixed potentials with respect to the reference node as set by those sources.
     
  8. Nov 25, 2014 #7
    I see. Thank you for the illustration. :) I shall try solving the question again.

    Just wondering, if I were to not use supernodes at all, is it generally okay for Node Voltage Analysis? This is just in case where I get confused in the exam and use supernodes inappropriately. :X (But I will still keep in mind on your advice on how to set the boundaries of supernodes. :D)
     
  9. Nov 25, 2014 #8
    Hmm.. I still got 3/16 as my answer. :(
     
  10. Nov 25, 2014 #9

    gneill

    User Avatar

    Staff: Mentor

    You'll find that you can't avoid using supernodes if there are voltage sources connecting two nodes (unless you choose an analysis method other than nodal analysis). When two nodes are connected by a voltage source there's no way to write an expression for the current through it in terms of the node potentials and a resistance because there's no resistance value to use.
     
  11. Nov 25, 2014 #10

    gneill

    User Avatar

    Staff: Mentor

    Type out your work so we can have a look.
     
  12. Nov 25, 2014 #11
    Here is my working: (I was typing out when you posted this. Haha.)

    21mynns.jpg

    Thanks! :D
     
  13. Nov 25, 2014 #12
    I see. Thank you for your advice. :D I will keep a lookout for those cases and apply supernodes appropriately.
     
  14. Nov 25, 2014 #13

    gneill

    User Avatar

    Staff: Mentor

    Your "supernode" equation is not correct; it has no term for the path through v1 and R1.

    But your supernode includes the reference node, so you do not have to write an equation for it. The second node to use is where R3, R4, and R5 come together (that is, v2).
     
  15. Nov 25, 2014 #14
    Oh gosh! @.@ Sorry. I made a careless mistake there. :( I have to add (v-v1)/1 in front of the first equation under SN.

    And hmm.. I shouldn't have written an equation for v cos it overlaps with my equation for the supernode..

    I finally got the answer~ Thank you very much!! ^^
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted