Or that the clock path be very slightly longer in propagation time than any of the data lines.That assumes that clock and date lines have the same length.
When a parallel bus was run on a mainframe backpanel, several identical twisted pairs with the same length were used to route the differential signals. Once terminated with wire wrap, the excess length was folded into the gaps between the connector blocks. To modify the back plane required access, carefully unfolding and lifting out the delay lines.We need a delay. Can you just run a wire around the inside of the case?