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Stack effect

  1. Nov 18, 2009 #1
    What is stack effect in cmos design and how would it affect the threshold voltages?
     
  2. jcsd
  3. Nov 19, 2009 #2

    es1

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    This sounds somewhat like a HW question.
    A "stack" is just two or more transistors in series. So think of a standard CMOS inverter but with two NMOS gates in series on the bottom half. Can you determine how doing that would effect the threshold of each transistor? Pay close attention to Vsb.
     
    Last edited: Nov 19, 2009
  4. Nov 20, 2009 #3
    Ok with two nmos in series, assuming their body is both grounded, Vt of the top nmos would increase since when a gate voltage is applied to the bot nmos, the source voltage (Vs) of the top nmos will be at a voltage Vgs higher than its body.

    But here comes the question, such a 'stack effect' with the increase in Vt of the first nmos would only happen when the bot nmos is turned on right?
     
  5. Nov 20, 2009 #4

    berkeman

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    Staff: Mentor

    What is the context of your question? What is the application?
     
  6. Nov 20, 2009 #5
    The stack effect on Vt for a two input NAND gate. (2 nmos in series for pull down) If I am understanding correctly, the Vt for the nmos on top would increase only during transitions where the bot nmos is on? cause if the bot nmos is off, the top nmos would also be grounded and stack effect would not have any effect on vt?
     
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