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Synchronous Counters

  1. Jul 29, 2007 #1
    First, I'll note that this is not a homework or project question - I'm studying for a test, and am trying to better understand the material.

    Note: I don't think that I'll need to know how to do up/down counters, although if you feel like explaining those, or pointing me in the right direction, that would be nice.

    I'm trying to understand how to answer questions of the following forms -
    "Design an up-counter which counts from 0 to 7"
    "Design an up-counter which counts from 0 to 6"
    "Design a down-counter which counts from 7 to 0"
    "Design a down-counter which counts from 6 to 0"

    Of course, these are four distinct cases -
    The first follows the natural states of a 3 bit implementation, counting up: 0-1-2-3-4-5-6-7-0-1-2....

    The second follows the natural states of a 3 bit implementation, counting up, until it reaches 6, at which point it skips the next natural state and goes directly back to 0: 0-1-2-3-4-5-6-0-1-2....

    The third follows the natural states of a 3 bit implementation, counting down:

    Finally, the fourth follows the natural states of a 3 bit implementation, counting down, except that it starts at 6, rather than 7, and the jump from 000 to 110 (6) isn't the normal progression.

    In all cases, I use D flip-flops and have a count_enable signal

    I understand the basics of counters, but don't really understand how to actually implement them. I know to do the Current State and Next State charts

    (i.e.) Current State Next State
    000 001
    001 010
    010 011
    011 100

    etc., and I know that there are xor equations involved in the next step.

    What are the real differences in design between up-counters and down-counters?

    What is done differently when doing a count that skips the next natural state (i.e. going from 110 back to 000, rather than to 111 next)?

    All of this might be hard to explain in a forum thread, so if anyone knows of a good website, pdf, ppt, etc. that would be helpful, that would be great. My book isn't really useful for this (or I can't really make sense of it, at least), and I've had trouble in my internet searches, but if you know of a good resource, I'd appreciate it.

  2. jcsd
  3. Jul 29, 2007 #2


    User Avatar

    Maybe you should look back to more abstract state machine theory.
    You clearly understand the evolution of states needed for each counter.
    There is no unique 'design' for a counter to perform any of those
    actions, though. The best design just depends on what tools you have to
    work with.

    Design with NAND gates only?
    Design with Verilog?
    Design with VHDL?
    Design with a PAL/PLD?
    Design with a FPGA?
    Design with J-K flip flops?
    Design with T flip flops?

    Certainly the concept of logic minimization does exist, and given
    particular design building blocks there probably is some 'most efficient'
    design for a given state machine, in terms of minimizing gates/parts,
    but if you're just trying to design something that is A start machine,
    there are lots of correct designs and maybe lots of 'best approaches'

    Sometimes the design with the least number of gates isn't the best
    because it may involve more levels of logic depth and hence may run
    more slowly than something that is wider and less deep.

    Have you ever looked at the data sheets for various decade counters
    in the TTL logic family? Many of those data sheets show you the INTERNAL
    logic that implements the counter, so you can get an idea of how
    the logic is designed.

    Also look at the application notes for PLDs / FPGAs about
    implementing various kinds of counters / state machines in those
    kinds of programmable devices you'll find a wealth of information on
    design options and their benefits / disadvantages.

    Sometimes it's best to implement a counter that counts in
    gray code instead of binary arithmetic since only one bit will change
    at a time for each state thus simplifying the logic and eliminating
    glitches due to cases where multiple bits are changing and in the
    process of the change there are invalid states that can be decoded
    because some bits change faster than others e.g. if you're not using
    clock synchronous logic on your state outputs but are decoding
    them unregistered.

    One way to make an arbitrary pattern of counts is a ROM that's
    preloaded with your desired pattern of count sequence and feed
    the ROM a state code on its address bits that indicates which
    input state is active and it'll look up the correct output state bits.
    The input state bits could be binary, gray code, one-hot, or whatever.

    Go to xilinx.com and download a lot of the xcell newsletters and application
    notes, and they'll talk about state machine design and counters in many.

    Also places like fairchild.com, ti.com, etc. for data sheets on various
    decade counters, etc.
  4. Jul 29, 2007 #3
    Thanks, xez
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