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T flip-flop counter using VHDL

  1. Nov 30, 2008 #1
    I have to design a counter using T flip-flops to count in the sequence 000, 100, 111, 010, 011, 000,.....(repeat).

    I think I got the code for the T flip-flop but not really sure and need some help implementing the counter with this.
    Any help would be great. Thanks

    //T flip-flop
    Code (Text):
    library ieee;
        use ieee.std_logic_1164.all;

    entity tff_sync_reset is
        port (
            data  :in  std_logic; -- Data input
            clk   :in  std_logic; -- Clock input
            reset :in  std_logic; -- Reset input
            q     :out std_logic  -- Q output

    end entity;

    architecture rtl of tff_sync_reset is
        signal t :std_logic;
        process (clk) begin
            if (rising_edge(clk)) then
                if (reset = '0') then
                    t <= '0';
                    t <= not t;
                end if;
            end if;
        end process;
        q <= t;
    end architecture;
  2. jcsd
  3. Dec 1, 2008 #2
    I think each TFF is used to hold a bit, so you will be using 3 TFFs. If the question was asking for synchronous counter, then the clocks of the TFFs are tied together. You will then draw a state-transistion table, then use k-map to implement the combination logic to set the input to the TFFs at each state.

    The input bit that goes into a TFF is usually not called 'data' but 'toggle'. When the 'toggle' bit is 1, the TFF toggles its bit.

    Your code for the TFF doesn't have this toggle bit. (It would be what you call 'data', but you didn't use it.)
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