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I have a verilog code for a simple 8-bit counter. I'm trying to build a testbench but for some reason it doesn't work. I'm using xilinx and when I run the simulation, the inputs work but the output doesn't work. It stays as XXX. Here is my verilog code and testbench.

testbench

I can't seem to find the reason why the output is no being displayed. I have tested someone else's code and the same happened. Could someone kindly give me a clue on what I'm doing wrong?

Code:

```
module counter(enable, reset, clk, out, AN, style);
input style; //to count up or down
input clk;
input reset;
input enable;
output [6:0] out; //output to display
reg[3:0] first; //to hold the output for first seven-seg
reg[3:0] second;//to hold the outputfor second seven-seg
reg[24:0] CLKCNTR; //clock counter
output [3:0] AN;//to indicate which seven-seg to use
always @(posedge clk)begin//mak it count when the clock ticks
CLKCNTR = CLKCNTR+1; //increment the clock counter by one until
if (CLKCNTR==25000000) //it reaches 25000000
begin
CLKCNTR=0; //reset the counter to loop
if (reset) //occurs only when reset is high
begin
first=0; //reset seven segment displasy if
second=0; //reset is high
end
else if (enable)
begin
if (style) //if counting up
begin
first = first+1;//increment first digit
if(first==10) //if it reaches 10, reset and increment next digit
begin
first=0;
second = second+1;
if(second==6) //if second digit reaches 6(one minute), reset
second=0;
end
end
else if (!style)//if counting down
begin
if (first>0)//decrement the first digit unitl it reaches zero
first=first-1;
else
begin
first=9;
if (second>0)
second=second-1;
else
second=5;
end
end
end
end
end
//instantiate the display module with the inputs and output
display D1(.clk(clk), .out(out),.AN1(AN), .ones(first), .tens(second));
endmodule
module display(clk, out,AN1, ones, tens);
input clk;
output reg[6:0] out;
//output reg[6:0] out2;
input [3:0]ones; //first digit(seven segment display)
input [3:0]tens; //second digit(seven segment display)
output reg [3:0] AN1; //to tell which seven segment display is to be turned on
reg[20:0] DSPCNTR; //display counter
initial begin
AN1[3:0] =4'b1011;//initialize the seven-seg displays
end
[email protected](posedge clk)
begin
DSPCNTR = DSPCNTR +1;//increment the counter of display counter until it reaches 25MHz
if(DSPCNTR == 250000)//that way the seven-segs are refreshed and we are able to see them change
begin
DSPCNTR = 0; //reset counter
AN1[2]=~AN1[2];
AN1[1]=~AN1[1];
if (AN1[1])
begin
case (ones)//case for first digit
0: out=7'b1000000;
1: out=7'b1111001;
2: out=7'b0100100;
3: out=7'b0110000;
4: out=7'b0011001;
5: out=7'b0010010;
6: out=7'b0000010;
7: out=7'b1111000;
8: out=7'b0000000;
9: out=7'b0010000;
default: out=7'b1111111;
endcase
end
else if (AN1[2])//case for second digit
begin
case (tens)
0: out=7'b1000000;
1: out=7'b1111001;
2: out=7'b0100100;
3: out=7'b0110000;
4: out=7'b0011001;
5: out=7'b0010010;
6: out=7'b0000010;
7: out=7'b1111000;
8: out=7'b0000000;
9: out=7'b0010000;
default: out=7'b1111111;
endcase
end
end
end
endmodule
```

Code:

```
module counter_tb;
// Inputs
reg enable;
reg reset;
reg clk;
reg style;
// Outputs
wire [6:0] out;
wire [3:0] AN;
// Instantiate the Unit Under Test (UUT)
counter uut (
.enable(enable),
.reset(reset),
.clk(clk),
.out(out),
.AN(AN),
.style(style)
);
initial begin
// Initialize Inputs
enable = 0;
reset = 0;
clk = 0;
style = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#3 reset =1;
#2reset = 0;
#2 style = 1;
#2 enable = 1;
#100 enable = 0;
#4 reset = 1;
#4 reset = 0;
end
always begin
#1 clk = ~clk; //clock toggles every strike
end
endmodule
```

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