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Trouble with 4 bit synchronous up counter

  1. Sep 21, 2005 #1
    I'm supposed to build a 4 bit synchronous up counter that counts in binary from 1-12 and restarts. I've made a circuit similar to the image shown below. My question is, what do i do to make it count from 1-12 instead of 1-16 and restart back at one?

  2. jcsd
  3. Sep 22, 2005 #2


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    You need to decode the output, and use the 12 output count to reset the flops. And you need to add logic to the output of the counter to basically add 1 to the output of the flops, so that instead of counting 0-11, it counts 1-12.
  4. Sep 22, 2005 #3


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    Or you could use the "set" function of the j/k on the LSB flop and the "reset" function of the j/k on the more significant bits when the output 12 is decoded. This will require the LSB flop to have slightly different input logic than the others. It's difficult (for me) to decide off the top of my head which is easier so you will have to. 1) build combinational logic to translate output, 2) change input logic of LSB flop to set

    Probably one requires more gates but two requires more creative design.
    But if you can design the clear logic you can design the set logic too.

    NOTE: If your flops actually have pre and clr inputs, which are not shown on your schematic, this task becomes much easier.

    Sucks that 12 is even... :)
  5. Sep 22, 2005 #4

    Oh crap, sorry about that. I found that image online as fast as I could and I didn't noticed it didn't include the pre and clr inputs. Here is the exact JK flip flop I'm using. It's a 74LS76N.


    Edit: Just to be a little more clear. I'm totally confused on how exactly to make this circuit count only to 12. I've got it counting up to 16, but the whole counting to 12 thing is totally over my head.
    Last edited: Sep 22, 2005
  6. Sep 22, 2005 #5


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    1100 is decimal 12 right? When the two most significant bits are 1, reset the counter and add one as berkeman suggest.
    Last edited: Sep 22, 2005
  7. Sep 22, 2005 #6


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    I'll try to provide some food for thought to point you in (hopefully) the right direction:

    When you say you want something to count from 1-12 what do you mean? What I think you mean is you want the system which currently exists and counts from 1-16 to count to 12 and then start over again at 1. Well, what input on your flip flop, regardless of the current flip flop state (aka the value of Q), allows you to start over again? Or to put it another way, what input regardless of current state and input puts the flip flop into a known state? So you'll want to do some thing with this input when the count reaches 12. But how do you know when it reaches 12? Well, how do you know when the count reaches 16? You must know how to do this because you say you have it counting to 16. How do you know? Using this information can you write a boolean logic equation that is true when the count is 16 and false other wise? Now try doing the same thing for count=12. Try to implement your equation in logic gates. So now you have a method for putting flip flops into known states (say the state where count=1 for instance) and a method for identifying when the count is 12...

    This is a side note, but from your circuit diagram and your the description of the count I think you are defining your states in a non-standard way. It doesn't really matter, any mapping is correct (as long as your consistent within the system) but you may confuse people who are used to doing it in the standard way. I didn't notice it myself in post #3. Anyway, to keep from getting confused just stick to your current system and I'll mention the standard way of doing it when your done.
    Last edited: Sep 22, 2005
  8. Sep 22, 2005 #7
    I know that my circuit is counting to 16 because the 4 LEDS that are connected to the ~Q outputs count from 0000 to 1111. The count reaches 16 when it is 1111 and the count reaches 12 when it is at 1100. Thats about all i know right now. I'm not sure either how to do the boolean expression with it.

    Edit: So from what I think you are saying, I should be using my resets. So should i just use the resets on the 3rd and 4th FF's?
    Last edited: Sep 22, 2005
  9. Sep 22, 2005 #8
    Ok I put in another AND gate and had the inputs from Q3 and Q4 go into the AND gate and the output of the AND gate went to the resets of Q3 and Q4. The only problem is that it counts from 0-11 and then resets back to the beginning. How can i get it to count up to 12??

    Edit: Alright I think i did this right now. On multisim it is counting to 12 then resetting. Here is the schematic. Can this be simplified more?


    Edit: I figured how to remove the inverter and the extra AND gate. Thx for all of the help guys!
    Last edited: Sep 22, 2005
  10. Sep 23, 2005 #9


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    There you go. When you experiment you are learning.

    Good luck.......Don
  11. Sep 26, 2005 #10
    Sorry it has taken this long, but I have a few suggestions that might be useful to you. First, you want a completely synchronous counter. This is the general rule for any time clock type logic (I assume that's what this is). The second circuit drawing you show is synchronous with respect to the count-up, but not for the resetting. You really don't need to use the "Preset" and "Clear" (they are asynchronous), this can be done with the same type of consideration as for the count-up, by driving the "J" and "K" at the proper times. I came up with a circuit that has three 2-Input_ANDs, and two 2-Input-ORs (or five 2-Input NANDs and an inverter) and doesn't need use the asynchronous controls. Here is what you need to do:

    First draw up a "truth table" for your four-stage counter, then 'cross-out' the values that are not used, ie. the 'zero' and the 'thirteen through fifteen' count values. Then, for each output bit, determine where the "transitions" are. Then, for each of these four output bits, define the value of the four bits in the step before the transition. (In a synchronous counter it is the preceding state that defines any transition --- ie., a state machine.) Once you have the driving conditions for each transition for an output, enter these into a four-variable map, and solve for the driving logic; for each respective flip-flop. (It turns out that the states can be controlled simply by toggling each flip flop each time a transition is needed. Also, the the lowest order output is a trivial case, and doesn't need this much consideration, and the second isn't much more complex.) (Also, remember that those "crossed out" count values can be used as "don't care" states.)

    Try it; I think you will see what I mean.

  12. Sep 30, 2005 #11
    I decided to show the easy way to design a synchronous counter. Remember, that in order to be synchronous, not only must its counts up be synchronous, but also must the count which carries over and back to the initial value. The first thing that we should do, is to make up a 'truth table' for all the possible count values. There are four variables that will always determine what the next count must be --- the four "Q" outputs from the four flip-flops that hold the count values. (Actually, there are five, if the 'count clock' is considered, however since the flip-flops here can be driven in a "toggle" manner, just by controlling the "J" and "K" inputs to these flip-flops, --- then the "clock" can be ignored, since it won't control directly these control signals to the "J" and "K". Whenever both "J" and "K" are 'one' to any flip flop, it will toggle, [at the next clock] so we simply must decide for each flip-flop, when it must be 'one' at both "J" and "K". [all other times, it will be 'zero' at both of these inputs, so that nothing will happen then.])

    In the first attachment, is drawn a 4-variable 'truth table'. Given in addition, is the 'decimal' equivalent for the sixteen values of four flip-flop outputs, just to make it easier to keep track of where we are. We note that, since count values "0", "13", "14" and "15" will not be used, these are shaded out.

    Next, we draw "parallel" tables for the control inputs to each of the flip-flops. Here, I have left out a table set for the "A" flip-flop, because it is a trivial case. It toggles every time, so its inputs are just tied to "one" (+5Vdc). Each of the remaining three parallel tables then has two columns, --- one for when the conditions needed for a "toggle" must be present, and one for the direction for the toggle. Actually, the "Dir" columns aren't absolutely necessary, but they make it more convenient, for two reasons. First, they can represent the exact relative times of the toggles, and second, they give us an indication that we haven't screwed up (by not always following a 'down toggle' with an 'up toggle' and vice versa).

    For the table of each needed output, we then put in an up or a down arrow at the point that the corresponding flip-flop must toggle. We put it across the "transition to the 'new state' because that is when the toggle must occur. If each up is followed by a "down" and each "down" by an "up", we are fairly sure that we have it right. Next, for each arrow, we put in a check (or the like). Here, we take care to put in the checks into the rows 'just ahead' of the anticipated toggles, because it is the "prior-state" conditions that control the toggles. (In essence, the "before-toggle" states are the (A, B, C and D) states of the flip-flops, while, the "after-toggle" states of each flip-flop can be called A", B", C" or D". Thus, we are looking for the A, B, C and D inputs that will give us the A", B", C" and D" flip-flop states. From this, we note that D->D" has two toggles per count cycle, C->C" has four and B->B" has six. ("A->A" naturally will have twelve, because it toggles every cycle.)

    The next step, is to enter the table values into a K-Map for each variable. Here, we show only for C" and D", because B" (similar to A") is very simple, and should be obvious. If "ordered" K-Maps, like the ones shown in attachment-one are used then, filling the maps is easy, because the values from each table column can simply be put into a corresponding "cell" of its map. (Each is numbered.) For each checked location in a table column, put a "one" (or whatever is desired) into the corresponding map cell.

    Next, we simply solve each K-Map to determine what the input logic to each count flip-flop must be. Note that several values of the original truth table are "forbidden" and thus will never occur (0, 13, 14 and 15). These are shown shaded in the maps. These can be used as 'don't care' states when the maps are solved --- thus they may be considered as either "zero" or "one"; whichever is convenient. Thus, when each map is solved, we get: A" = 1 (Every clock cycle) B" = A, C" = AB + CD and D" = ABC +CD.

    Using the solutions derived, we can get a circuit like the one in attachment 2. (We could also use four NANDs and an Inverter.)

    Finally, we should run through each state to verify what the transitions will be. Attachment 3 shows these transitions. We note that a power spike or something like it could put the counter, like any counter, into a "forbidden state (like any clock when the power is lost).This figure shows what would happen in such case. The circuit doesn't stay in the forbidden state, but , of course, count reference would be lost until the counter is re-initialized. We also note, that the counter that we have designed is basically like that of the standard twelve-hour time-of-day clock.

    I hope that this has been useful. This method can be used with basically any synchronous sequencer/counter. Tomorrow (or the next day) I shall probably bring another example
    --- an "Excess-three" counter.


    Attached Files:

  13. Oct 1, 2005 #12
    Here is another example. This one is an "Excess-Three" counter. Basically, this is a variation of the BCD (Binary Coded Decimal) counter. The main problem with the BCD representation is the fact that subtraction cannot be easily done with it using the usual means of finding the "complement" of the value. (Most computers today do the arithmetic operations by first converting to Binary, but what if there is no full-fledged computer available for this, but that a simple Excess-Three adder can be provided? For this sometimes the Excess-Three code is used. It uses the basic four-bit Hex-type representation, however rather than using the first ten values (0 through 9), The values are all augmented by three (ie 0 -> 3, 1-> 4, etc). Thus, rather than using the first ten values from the Hex code, the middle ten are used.

    With these, it is easily seen that the values are now self complementing. Just by inverting all the bits in a four-bit Excess-three representation, we can get its 'nines-complement'. Thus we can now perform subtraction on its values simply with an adder and by inverting the bits in the number.

    To be sure, this representation has drawbacks also; for example, finding 0ff-the-shelf displays, and other matching components can be a problem. Also, Excess-Three is not a "Weighted Code". That is to say, we can no longer define the values of each "digit" simply by adding up the values of its four outputs --- as with Hex or BCD. (There are sone other complementable codes that are weighted.)

    That said, an Excess-three 'counter' is shown implemented in the accompanying attachments, just as was done with the 'twelve-hour-clock type counter. Note that the value for "zero" is now "0011", and that the first and the last three Hex values are now 'forbidden' or 'don't care' values.


    Attached Files:

  14. Mar 27, 2008 #13
    74ls76n Ic

    I designed a binary counting circuit in multisim using individual JK flip flops and it worked perfectly. However when trying to use the 74LS76N IC (Dual JK flip flops on one IC) to do the same thing i couldnt get it to work. I connected it exactly the same way, not sure why one wud work and not the other?
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