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TTL Gate Circuits

  1. Jul 16, 2012 #1
    Why do TTL integrated circuits assume unconnected inputs to be at logic level HIGH? Does the answer lie in the circuitry itself or some other factor?
  2. jcsd
  3. Jul 16, 2012 #2


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    In the diagram, the inputs are only low if current flows out of the device at A or B. Otherwise, they are high.

    If either of the inputs is grounded, then the output transistor will not get base current so the output will be high.
    Only if both inputs are not grounded, ie high, then the output will be low.

    This is a NAND gate, but the input logic is similar for other TTL devices
  4. Jul 16, 2012 #3


    Staff: Mentor

    Not sure you'll get a definitive answer but it makes sense for multiple input gates to leave unconnected gates as high. As an example, a 4 input AND gate where you only need 3inputs you'd set the fourth one high.
    Last edited: Jul 17, 2012
  5. Jul 16, 2012 #4
    I'm not that familiar with the internal circuitry of TTL gates yet. In the diagram, Vcc is one of the inputs right? Where is the other one? Do A and B represent the output terminals?

    So, if the input is grounded we know that it goes through a certain circuit so we expect its output voltage to be low? Otherwise, it is high?
  6. Jul 16, 2012 #5


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    No, the inputs are A and B, but the output transistor gets its base current from Vcc via the base-collector diode of the odd-looking transistor at the left and the series resistor at left. The output is "Q".

    Grounding either emitter robs the output transistor of its base current by providing a single diode path to ground for the base current of the output transistor, while the path through the output transistor's base involves two diodes and two diode drops.

    So, all the base current goes via the left path.
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