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TTL gate

  1. Aug 22, 2006 #1
    Is it true that a "high" input of a TTL gate shouldn't be left floating but instead connected to +Vcc through a pullup resistor because this way the propagation delay time is reduced and less noise is captured?
    If that's true, should a pullup resistor be used when connecting the input of a TTL gate to the output of an open-collector driving gate?
     
  2. jcsd
  3. Aug 22, 2006 #2

    berkeman

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    Unused inputs on basically any logic family should not be left floating. The issues has to do with power consumption and noise. If the input is used (connected to some other gate's output), then a pullup resistor is only needed if the output driving it is open collector.
     
  4. Aug 22, 2006 #3

    chroot

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    Floating inputs have the potential of rapidly (and randomly) switching from the high to low states due to noise. Everytime they flip, all the on-chip capacitance they're driving has to be charged or discharged, wasting power.

    - Warren
     
  5. Aug 22, 2006 #4
    I see. Thanks for your answers.
     
  6. Aug 22, 2006 #5

    NoTime

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    It's a good practice, but this is mostly a non issue in the case of TTL.
    However, for other logic familys, like CMOS, it is extremly important to not leave inputs flaoting.
     
  7. Aug 23, 2006 #6

    chroot

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    Of course, who actually uses BJTs for digital output drivers anymore? Anyone at all? Any digital device designed in the last couple of decades is going to have CMOS logic.

    - Warren
     
  8. Sep 4, 2006 #7
    One little additional point. How an input is "tied" also depends on what that input is to do logically. "Unused" doesn't mean that the input isn't doing anything --- all inputs will do something whether we ignore them or not. Thus, an unused input to an AND/NAND must be tied (through a pullup) to Vcc (a "1" value), and likewise an unused OR/NOR input must be tied to Ground.

    KM
     
  9. Sep 7, 2006 #8

    berkeman

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    Interesting. I hadn't heard that before. Why the directional preference for the different function gates?
     
  10. Sep 7, 2006 #9

    chroot

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    berkeman,

    He's simply saying that if you have a 3-input AND gate and want to leave one of its inputs unused, you need to tie it high to preserve the logical AND function between the remaining two inputs. Likewise, if you want to leave an input of an OR gate unused, you need to tie it low.

    Neither of these observations have anything to do with the electrical behavior of the CMOS transistors used in making the gate, and are therefore pretty much irrelevant.

    - Warren
     
  11. Sep 7, 2006 #10

    berkeman

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    OH! Now I get what he was saying. I was thinking unused gate, not just unused individual inputs. That clears it up. Thanks!
     
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