Pullup Resistors & TTL Gates: Reducing Delay and Noise

In summary: Interesting. I hadn't heard that before. Why the directional preference for the different function gates?He's simply saying that if you have a 3-input AND gate and want to leave one of its inputs unused, you need to tie it high to preserve the logical AND function between the remaining two inputs. Likewise, if you want to leave an input of an OR gate unused, you need to tie it low.
  • #1
antonantal
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Is it true that a "high" input of a TTL gate shouldn't be left floating but instead connected to +Vcc through a pullup resistor because this way the propagation delay time is reduced and less noise is captured?
If that's true, should a pullup resistor be used when connecting the input of a TTL gate to the output of an open-collector driving gate?
 
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  • #2
Unused inputs on basically any logic family should not be left floating. The issues has to do with power consumption and noise. If the input is used (connected to some other gate's output), then a pullup resistor is only needed if the output driving it is open collector.
 
  • #3
Floating inputs have the potential of rapidly (and randomly) switching from the high to low states due to noise. Everytime they flip, all the on-chip capacitance they're driving has to be charged or discharged, wasting power.

- Warren
 
  • #4
I see. Thanks for your answers.
 
  • #5
It's a good practice, but this is mostly a non issue in the case of TTL.
However, for other logic familys, like CMOS, it is extremely important to not leave inputs flaoting.
 
  • #6
NoTime said:
It's a good practice, but this is mostly a non issue in the case of TTL.
However, for other logic familys, like CMOS, it is extremely important to not leave inputs flaoting.

Of course, who actually uses BJTs for digital output drivers anymore? Anyone at all? Any digital device designed in the last couple of decades is going to have CMOS logic.

- Warren
 
  • #7
One little additional point. How an input is "tied" also depends on what that input is to do logically. "Unused" doesn't mean that the input isn't doing anything --- all inputs will do something whether we ignore them or not. Thus, an unused input to an AND/NAND must be tied (through a pullup) to Vcc (a "1" value), and likewise an unused OR/NOR input must be tied to Ground.

KM
 
  • #8
Kenneth Mann said:
One little additional point. How an input is "tied" also depends on what that input is to do logically. "Unused" doesn't mean that the input isn't doing anything --- all inputs will do something whether we ignore them or not. Thus, an unused input to an AND/NAND must be tied (through a pullup) to Vcc (a "1" value), and likewise an unused OR/NOR input must be tied to Ground.

KM
Interesting. I hadn't heard that before. Why the directional preference for the different function gates?
 
  • #9
berkeman,

He's simply saying that if you have a 3-input AND gate and want to leave one of its inputs unused, you need to tie it high to preserve the logical AND function between the remaining two inputs. Likewise, if you want to leave an input of an OR gate unused, you need to tie it low.

Neither of these observations have anything to do with the electrical behavior of the CMOS transistors used in making the gate, and are therefore pretty much irrelevant.

- Warren
 
  • #10
OH! Now I get what he was saying. I was thinking unused gate, not just unused individual inputs. That clears it up. Thanks!
 

1. What are pullup resistors and why are they used in TTL gates?

Pullup resistors are resistors that are connected between a signal line and a positive voltage source. They are used in TTL gates to ensure that the signal line is pulled up to a high voltage level when there is no input signal present. This helps to reduce noise and prevent the gate from mistakenly interpreting a floating signal as a logic level.

2. How do pullup resistors help to reduce delay in TTL gates?

Pullup resistors can help reduce delay in TTL gates by providing a strong and stable voltage level for the input signal to be compared against. This reduces the time it takes for the gate to determine the correct logic level and can improve the overall speed and performance of the gate.

3. Can pullup resistors eliminate all noise in TTL gates?

No, pullup resistors can help reduce noise in TTL gates but they cannot eliminate it completely. Other factors such as the quality of the gate itself and external interference can also contribute to noise in the system.

4. What is the recommended value for pullup resistors in TTL gates?

The recommended value for pullup resistors in TTL gates is typically between 1-10k ohms. However, the exact value may vary depending on the specific circuit and application. It is important to consult the gate's datasheet or perform calculations to determine the appropriate value for the pullup resistor.

5. Are pullup resistors necessary for all TTL gates?

No, not all TTL gates require pullup resistors. Some TTL gates may have built-in internal pullup resistors, or they may not be needed depending on the circuit design and input signals. It is important to consult the gate's datasheet and understand the specific requirements for each gate in a circuit.

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