Type of back-gate Si on FET

  1. Hi,

    I fabricated a very simple back-gate FET.

    I used highly Boron doped (so, P-type) Si wafer as a gate and then, grown SiO2 thermally as a dielectric. And, deposited N-type semiconductor followed by Au/Cr deposition as electrodes (source and drain).

    And I measured Ids-Vds and Ids-Vg. The results show the graphs of typical P-type semiconductor, even though N type semiconductor was used.

    I'm struggling to understand it but haven't yet.

    Is it possible this is because of highly doped P-type Si gate?

    (I looked for several reference and found that all used the same types of semiconductor and gate (i.e. highly doped n type Si gate + n-type semiconductor or highly doped p type Si gate + p-type semiconductor)

    Or is there anything I should check?

    Thank you.
    Last edited: Aug 26, 2011
  2. jcsd
  3. By backgate FET do you mean there is electrode in the channel for threshold voltage control?
    Can you describe the Ids-Vg(s?) test circuit?

    You didn't mention the body connection. You might want to check that.
  4. Thanks for your comment, es1.

    the attached picture shows the device.
    (my goal is to get electrical characteristics for N-type semiconductor)

    I believe that 'source' acted as a common electrode but I'm not sure I drew the connections between gate-source and drain-source correctly because I used pre-setting for measurement.

    Attached Files:

    Last edited: Aug 29, 2011
  5. Hi Can you provide the following.
    What is the test circuit ?
    What is the gate oxide thickness?
  6. Dear, rakeshgarg123

    Unfortunately, I don't know the test circuit exactly

    I used HP4156A analyzer and default setting for FET.

    SiO2 thickness is 100 nm.

    Is this not enough to understand my problem?
  7. Sorry slkms1. I am not familiar with that structure of a FET so I don't think I'll be able to help much after all.

    It kind of looks like a more typical FET, but just upside down and possibly without substrate. Is that right? Or maybe the blue boxes represent what would typically be considered the substrate?

    One thing that seemed off to me. The channel SI between the source and drain is n-type according to the drawing label. Isn't that consistent with the PMOS (I assume that's what is meant by p-type) behavior you measured?
    Last edited: Aug 30, 2011
  8. After rereading your post I am pretty sure you did build a PMOS.

    You have an n-type channel and metal barrier diodes at the S and D terminals.
    I have the distinct feeling that I am missing something obvious but I am pretty sure this is consistent with a PMOS.

    And it looks like the HP4156A agrees.

    See the PMOS vs NMOS cross sections here:
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