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Typical full adder gate delay

  1. Nov 14, 2015 #1
    • Member warned to use the formatting template for homework posts.
    Hi guys,

    I was just wondering, I'm designing a full adder for a bitslice of a 16 bit ALU.

    I have SPICED my design and I am getting a propagation delay for the AND mode between the two bits of about 70ps.

    I'm working in a low voltage 90nm process.

    Am I in the right ballpark in terms of propagation delay? or am I absurdly off? What is a typical propagation delay for a full adder (order of magnitude).

    Thanks
     
  2. jcsd
  3. Nov 14, 2015 #2
    If I recall correctly (it's been a while, so I might be off), the delay for the entire adder circuit is usually in hundreds of nanoseconds, and individual operations (AND and XOR) take about 40 to 50 nanoseconds each (with 45nm technology).

    But as you might know already, gate delays depend on a number of factors such as the input capacitance, threshold and supply voltages etc. So there might be nothing wrong with the numbers that you have obtained.
     
  4. Nov 14, 2015 #3

    mfb

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    Staff: Mentor

    45-50 nanoseconds for individual operations would surprise me. Even with an extremely long pipeline a CPU has to get those operations done within a cycle, and in 2008 they certainly had more than 20 MHz.
     
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