Understanding Basic S-R Latch

1. Nov 17, 2012

SpaceCreature

I have a question about S-R latch for a specific diagram below (no, this is NOT a homework question).

Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be? I know, for example, that if R = 0, the output of AND will be 0, because both inputs need to be 1 or high for the output to be 1. I'm guessing the answer is no, the circuit does not know what the output will be with one input because if R = 1, how do we know what the second input will be?

What boggles my mind is this: let's pretend that R always gives its output first, because for some reason there is a delay in S. How is this possible? How can there even be an output for either AND gate if the AND gate needs two inputs to make a decision about an output?

http://img839.imageshack.us/img839/3791/latchq.jpg [Broken]

Last edited by a moderator: May 6, 2017
2. Nov 18, 2012

Ratch

SpaceCreature,

2-input AND gates have 4 states; 00, 01, 01, 11 period. It bases its output solely on those states. The AND gate neither "knows" nor does it have any cognizance of what the next state will be. It operates on what is applied to the input at the current time.

What is the problem? The 2-inputs are going to be either 1 or 0. The AND gate will base its output on those current inputs.

Ratch

3. Nov 19, 2012

LawRooney

A high output simply means a current is flowing through the wires. If the S gate is slower than the R gate, than the R gate will be receiving a low signal from one of its outputs, and will produce a 0.

4. Nov 19, 2012

Staff: Mentor

In a logic gates arrangement, at least those you will be working with, the signal at every point and on every wire is at all times either a 1 or else it's a 0, there are never any "undecided" or "still thinking about it" or "wait, I'm not ready yet" logic levels.

If a 2-input AND gate on one input has a 0, neither you nor the gate needs to take into consideration what is on the other input—the output of that AND gate is already determined to be 0 so the electronics is designed to make the output a 0.