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Understanding The FinFET

  1. Dec 12, 2013 #1
    Greetings forum!

    I want to discuss the characteristics and design of the FinFET device. I am a first year electrical engineering student and recently began understanding the importance of multi-gate devices in the future of transistors. The advantages of FinFETs over traditional planar transistors are well now well known. As transistors decrease in size, they tend to exhibit several short channel effects (SCE). FinFET design tends to reverse these SCEs while allowing transistor channel lengths to still decrease. One important SCE that the FinFET overcomes is the unwanted sub-threshold current leakage. What I don't really understand is HOW. I haven't really been able to find a clear answer to this in my research of FinFETs.​
    As I understand it, the traditional planar cmos transistors have source and drains that are driven deeply into the substrate. The gate however has an effective depth into the substrate over which its field can control the drain current. Far away from the gate however, there can still be some current that flows from source to drain for high enough drain voltages. The use of ultra thin channels rids transistors of a lot of this unwanted current. Then, introduction of double gate transistors also seemed to reduce leakage. FinFETs have great electrostatic control over the channel region because of the increased surface area of the gate over the channel. As well as having a very thin channel (fin) such that there is no silicon "too far" away from the gate.
    What I don't understand is how obtaining greater electrostatic control of the channel reduces sub-threshold current leakage for smaller and smaller channel lengths. The subthreshold barrier that prevents current flow in the OFF state is made thinner as the source and drain are placed closer and closer together such that electrons can tunnel through it. So people started increasing the doping of the channel to increase the size of the depletion layer and therefore increase the height of the potential barrier, but this came at a price since a higher applied threshold voltage was required. Another direction taken was the FinFET design. I don't really understand how wrapping the gate around the channel would change this leakage since you still have a source and drain that are placed really closely together, there should still be problems with the diminished potential barrier. I understand how there is better response time, and a lower threshold voltage, but I don't understand why there is less leakage. Can someone enlighten me on this matter?​

  2. jcsd
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