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Verilog ALU/state machine help

  1. Dec 10, 2011 #1
    1. The problem statement, all variables and given/known data
    The problem statement for the project is:
    Your are to build and control a Functional Unit (FU) based on the C program below. The FU has to handle 8 bit negative numbers and does the following operations: 1 power operation A^B note that B cannot be negative. 2 it can do addition of two numbers. 3 it can do bitwise OR operation.



    2. Relevant equations
    C program is as follows:
    void problem3_4()
    {
    int i;
    int count;
    int sum; //must be shown on a seven segment display
    /*these values can be considered inputs. To test your program make these values parameters and set them to 4, but make your design robust enough to handle other values*/
    int max1;//this is an unknown value that happens at runtime

    sum = 1;
    for(i=1;i<max1;i++)
    {
    //depending on what state the FU is in one of these three operations will //happen
    sum=sum^i;
    sum=sum+i;
    sum=sum|0x80;
    }
    }




    3. The attempt at a solution



    Here is what I have so far:

    module Lab7(clk, reset, enA, enB, enC, s, ctl, in1, displayOut1, displayOut2, displayOut3);
    input [3:0]in1;
    input [1:0]ctl;
    input clk;
    input reset;
    input enA;
    input enB;
    input enC;
    input s;
    wire [3:0]aluOut;
    output [6:0] displayOut1, displayOut2, displayOut3;
    wire clk, reset, enA, enB, enC, s;
    wire [3:0] in1;
    wire [1:0]ctl;
    wire [6:0] displayOut1, displayOut2, displayOut3;
    wire[3:0] temp_displayOut1;
    wire [3:0] temp_displayOut2;
    wire[3:0] temp_displayOut3;
    wire[3:0] temp_inB;
    Mux mux1(in1, temp_displayOut3, temp_inB);
    Reg reg_a(clk, in1, reset, enC, temp_displayOut1);
    Reg reg_b(clk,temp_inB, resest, enC, temp_displayOut2);
    Reg reg_c(clk, outAlu,reset,enC,temp_displayOut3);
    alu alu_1(s, reg_a, reg_b, aluOut);

    SevenSegmentDisplayDecoder a1(displayOut1,temp_displayOut1);
    SevenSegmentDisplayDecoder a2(displayOut2,temp_displayOut2);
    SevenSegmentDisplayDecoder a3(displayOut3,temp_displayOut3);

    endmodule


    module alu(a, b, ctl_1, outAlu);

    input [7:0] a;
    input [7:0] b; // port A,B
    output [3:0] outAlu; // the result
    input [1:0] ctl_1; // functionality control for ALU
    wire ctl_1;
    wire [3:0]a;
    wire [3:0]b;
    reg [3:0]outAlu;

    always@(ctl_1 or a or b)
    begin
    case (ctl_1)
    2'b00: outAlu <= a&b;
    2'b01: outAlu <= a|b;
    2'b10: outAlu <= a+b;
    2'b11: outAlu <= a-b;
    endcase
    end

    endmodule

    module SevenSegmentDisplayDecoder(ssOut, nIn);
    output reg [6:0] ssOut;
    input [3:0] nIn;

    // ssOut format {g, f, e, d, c, b, a}

    always @(nIn)
    begin
    case (nIn)
    4'h0: ssOut = 7'b0111111;
    4'h1: ssOut = 7'b0000110;
    4'h2: ssOut = 7'b1011011;
    4'h3: ssOut = 7'b1001111;
    4'h4: ssOut = 7'b1100110;
    4'h5: ssOut = 7'b1101101;
    4'h6: ssOut = 7'b1111101;
    4'h7: ssOut = 7'b0000111;
    4'h8: ssOut = 7'b1111111;
    4'h9: ssOut = 7'b1100111;
    4'hA: ssOut = 7'b1110111;
    4'hB: ssOut = 7'b1111100;
    4'hC: ssOut = 7'b0111001;
    4'hD: ssOut = 7'b1011110;
    4'hE: ssOut = 7'b1111001;
    4'hF: ssOut = 7'b1110001;
    default: ssOut = 7'b1001001;
    endcase
    ssOut = ~ssOut;
    end
    endmodule


    module Reg (clk, in, reset, en, out);
    input [3:0] in;
    input clk;
    input reset;
    input en;
    reg out;
    output [3:0]out;
    always @ (posedge clk or negedge reset)
    begin
    if (reset == 1'b0)
    out = 4'b0000;
    else
    begin
    if(en==1'b1)
    out = in;
    end
    end
    endmodule

    module Mux(s,d, b, e);

    input [7:0]d;
    input [7:0]b;
    input s;
    output [3:0]e;
    wire s;
    wire [3:0]d;
    wire [3:0]b;
    reg e;
    always @(s or d or b or e)
    begin
    if(s==1'b0)
    e=d;
    else
    e=b;
    end

    endmodule

    I'm not sure how to implement the state machine, handle negative numbers (I think twos complement), and the power function.
    1. The problem statement, all variables and given/known data



    2. Relevant equations



    3. The attempt at a solution
     
  2. jcsd
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