Verilog and gtkwave?

  • Thread starter Molecular
  • Start date
  • #1
Molecular
29
0
Hey guys, I've recently started poking around with verilog code and I've made a few programs now and I really want to get a .vcd file or something similar out of my programs so that I can use gtkwave to analyze the program flow.

The thing is, no matter what I do, no .vcd file is generated anywhere. As far as my understanding there are two ways I can do this, by either

a) Adding

initial begin
$dumpfile("file.vcd");
$dumpvars(0);
end

in my code, something which first gave a bunch of errors and suddenly the errors stopped, but no .vcd file was generated, or

b) running the vvp file like so:

$ vvp testbenchfile -vcd

which again, gave me no vcd file to run with gtkwave.

At one point I even found some guys code on the internet and copypasted it to make sure I wasn't doing something wrong, but this didn't give me any vcd file either even though it appearantly did for him. I'm using icarus iverilog, if that makes any difference. Any help would be greatly appreciated, as I have nobody else to ask.
 

Answers and Replies

  • #2
Molecular
29
0
Nevermind figured it out, didn't realize the vcp file wouldn't be dumped until I actually run the output from the first simulation.

I feel stupid now ^^
 
  • #3
rickyrockrat
1
0
Here's an example test module that generates the .vcd file. Took we a while to figure out that these:
$dumpfile("test.vcd");
$dumpvars(0,test);
produce the output, and the simulation must be run (see the finished keyword).

module test;

/* Make a reset that pulses once. */
reg reset = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0,test);

# 17 reset = 1;
# 11 reset = 0;
# 29 reset = 1;
# 5 reset =0;
# 513 $finish;
end

/* Make a regular pulsing clock. */
reg clk = 0;
always #1 clk = !clk;

wire [7:0] value;
counter c1 (value, clk, reset);

initial
$monitor("At time %t, value = %h (%0d)",
$time, value, value);
endmodule // test
 

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