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Verilog help

  1. Mar 12, 2004 #1
    my goal is to make a mod 60 counter using mod10 and mod6. Both counters have a clk input.

    Mod10 will count and will produce a cout which will carry to mod6. At this moment, mod10 will be 0 while mod6 is 1 which is 10. This will continue to 59.

    I need serious help on how to connect them together. For the clk parameter, what should I enter?
     
  2. jcsd
  3. Mar 15, 2004 #2
    In the testbench? I don't quite understand.....
     
  4. Mar 15, 2004 #3

    chroot

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    It would seem the mod 6 counter should be clocked by the overflow of the mod 10 counter.

    - Warren
     
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