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Verilog help

  1. Apr 15, 2005 #1
    I have a clock module that divides a 500mhz signal to a 200hz signal, and another module that is suppose to use the 200hz clk signal to drive 4 multiplexed 7segment display. My question is how do I input the clock module signal into the 7segment display module?
  2. jcsd
  3. Apr 18, 2005 #2
    What is the "another module" doing? Is it using the 200hz to cycle the 4 seg's?

    If so i'd use a flip flop as a 2 output counter (using Q and clk). Slight risk of race hazards but affordable at these frequencies.
  4. Apr 18, 2005 #3


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    The clock enters the module like any other signal. It should be declared as an input. If you use the signal as the argument in an always block (i.e. always(@posedge clk)), the synthesizer will know it's a clock. You do not have to do anything special to declare that an input signal is a clock; it's a clock if you use it as a clock.

    - Warren
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