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Verilog language question

  1. Feb 23, 2004 #1
    Say I have 3 modules and I want them to connect them together (make them work together. Ie, output of one module would go into another etc.), how would I do this in verilog?
     
  2. jcsd
  3. Feb 23, 2004 #2

    chroot

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    Create a top-level module that instantiates each of the three modules, and connects them with wires.

    - Warren
     
  4. Feb 23, 2004 #3
    instantiates ?[?] [b(] U mean create a 4th module that connects the 3 modules together with wire? Can u elaborate on the "wire" part?
     
    Last edited: Feb 23, 2004
  5. Feb 23, 2004 #4

    chroot

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    Yes, make a top level module which creates instances of the three lower modules.

    The "wire" keyword, surprisingly, makes wires.

    Here's a simple example with two modules, sub_a and sub_b, and a toplevel module which connects their inputs and outputs.

    module sub_a ( in, out );

    input in;
    output out;

    ....

    endmodule

    module sub_b ( in, out );

    input in;
    output out;

    ...

    endmodule

    module toplevel;

    wire one;
    wire two;

    sub_a sub_a_instance ( .in(one), .out(two) );

    sub_b sub_b_instance ( .in(two), .out(one) );

    endmodule
     
  6. Feb 23, 2004 #5
    My interpretation of ur code sub_a input is wired to sub_b output. Am I right?
     
  7. Feb 23, 2004 #6

    chroot

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    Yup, it just wires the inputs of each to outputs of the other. Of course the names are not exactly well-chosen. I just wanted to demonstrate the concept.

    - Warren
     
  8. Feb 23, 2004 #7
    Thanks you've cleared it up alot. I have another problem. I'm trying to write a code for a chip that has 3 modules and the output of those three modules are connected to an AND gate. How do I go about doing that??
     
  9. Feb 23, 2004 #8

    chroot

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    ...

    wire sub_1_output;
    wire sub_2_output;
    wire sub_3_output;

    wire and_output;

    and and_gate (and_output, sub_1_output, sub_2_output, sub_3_output);

    ...

    - Warren
     
  10. Feb 24, 2004 #9
    now that i have a one bit ALU, how would I link 4 of them together for a 4bit ALU? same method?
     
  11. Feb 25, 2004 #10
    yep, just be careful not to mix up the carry signals.....
     
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