Verilog Serial Adder in Behavioral Description

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Homework Statement


My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.

I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:

Inputs for the shift register are: Si, CLK, Reset

Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)

Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.


The Attempt at a Solution



Code:
//Shift Register Module
module shift_register_beh (So, D, Si, Clk, RES);
output [7:0] D;
output So;
input Si, Clk, RES;
reg [7:0] D;

assign So = D[0];
always @ (negedge Clk)
begin
D <= {Si, D[7:1]};
end
endmodule

//Full Adder Module
module full_adder_beh (S, Co, A, B, Ci);
output S, Co;
input A, B, Ci;

assign {Co,S} = A + B + Ci;
endmodule

//D Flip-Flop Module
module D_flip_flop_beh (Q, D, Clk, RES);
output Q;
input D, Clk, RES;
reg Q;

always @ (negedge Clk or posedge RES)
begin
if(~RES) Q <= 1'b0;
else Q <= !D;
end
endmodule
 

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