Verilog Serial Adder in Behavioral Description

[pags920]

Homework Statement

My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.

I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:

Inputs for the shift register are: Si, CLK, Reset

Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)

Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.

The Attempt at a Solution

//Shift Register Module
module shift_register_beh (So, D, Si, Clk, RES);
output [7:0] D;
output So;
input Si, Clk, RES;
reg [7:0] D;

assign So = D[0];
always @ (negedge Clk)
begin
D <= {Si, D[7:1]};
end
endmodule

//Full Adder Module
module full_adder_beh (S, Co, A, B, Ci);
output S, Co;
input A, B, Ci;

assign {Co,S} = A + B + Ci;
endmodule

//D Flip-Flop Module
module D_flip_flop_beh (Q, D, Clk, RES);
output Q;
input D, Clk, RES;
reg Q;

always @ (negedge Clk or posedge RES)
begin
if(~RES) Q <= 1'b0;
else Q <= !D;
end
endmodule

 

[KataKoniK]

//Test Bench
module test_bench;
reg Si, Clk, RES;
wire So;
wire [7:0] D;
shift_register_beh uut (So, D, Si, Clk, RES);

initial
begin
Si = 1'b1;
Clk = 1'b0;
RES = 1'b0;
#5 Si = 1'b0;
#5 Si = 1'b1;
#5 Si = 1'b0;
end

always #10 Clk = ~Clk;

initial
begin
$dumpfile("test_bench.vcd");
$dumpvars(0, test_bench);
end

endmodule

it is important to approach the design of a serial adder in a systematic and logical manner. The first step would be to fully understand the functionality and operation of each individual module (shift register, full adder, and D flip-flop) and how they will work together to create the serial adder.

Once the individual modules have been studied and understood, the next step would be to design a high-level block diagram of the serial adder, showing the inputs and outputs of each module and how they are connected. This will help to visualize the overall design and ensure that all necessary connections are made.

Next, the shift register module can be designed. The inputs (Si, CLK, Reset) and outputs (So, D7-D0) have already been defined, so the focus would be on creating the logic for the shift register. The provided attempt at a solution looks correct, but it would be beneficial to simulate and test the module to ensure its functionality.

Moving on to the full adder module, the inputs (A, B, Ci) and outputs (S, Co) have been defined. It is important to consider how the full adder will be used in the serial adder and how the carry output will be handled.

The D flip-flop module is relatively simple, with the input (D) and output (Q) already defined. It is important to carefully consider the clock and reset signals to ensure proper functionality.

To approach designing a test bench, it would be helpful to first list out the desired test cases and expected outputs. This will guide the creation of the test bench and help to verify the functionality of the serial adder. It may also be helpful to use a waveform viewer to visualize the inputs and outputs during simulation.

In summary,