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Verilog testbench timing diagram

  1. Oct 20, 2013 #1
    1. The problem statement, all variables and given/known data

    As part of a lab, we developed a 7400 series and flashed an fpga based on a schematic.

    After going through the analysis process, the present state, next state, and a simplified state table was produced.

    J = (YB')'
    K = (BX)'
    T = (A'X)'

    J(t+1) = (YB')'A' + (BX)A
    T(t+1) = (A'X)'B' + (A'X)B

    Semplified State Table
    PS | XY= 00 01 10 11
    AB | AB AB AB AB
    ---------------------------
    00 | 11 01 10 00
    01 | 10 10 11 11
    10 | 01 01 01 01
    11 | 00 00 10 10


    The 7400 series followed through the state table. After getting the verilog working, it to followed the state table. Here is the verilog module:

    Code (Text):

    module lab3_mod(A_out, Ab_out, B_out, Bb_out, x_in, y_in, reset, clk);
      input x_in, y_in, reset, clk;
      output reg A_out, B_out;
      output Ab_out, Bb_out;
     
      wire J_in, K_in, T_in;
     
     
     
        assign J_in = ~(y_in & ~B_out);
        assign K_in = ~(x_in & B_out);
        assign T_in = ~(~A_out & x_in);
       
      always @ (posedge clk or negedge reset)
      if(~reset)
        begin
          A_out <= 1'b0;
          B_out <= 1'b0;
        end
      else
        begin
          case({J_in, K_in})    
            2'b00 : A_out <= A_out;
            2'b01 : A_out <= 1'b0;
            2'b10 : A_out <= 1'b1;
            2'b11 : A_out <= ~A_out;
          endcase
          case(T_in)
             
            1'b0 : B_out <=  B_out;
            1'b1 : B_out <= ~B_out;

          endcase
     
       end
        assign Ab_out = ~A_out;
        assign Bb_out = ~B_out;
       
    endmodule
     
    We were pressed for time and did not fully develop a test bench during lab. Afterwords, I went back and tried to walk through the state table in the test bench. Here is the test bench:

    Code (Text):


    `timescale 1ns/1ns
    module lab3_mod_testbench();
        reg x_in, y_in, reset, clk;
        wire A_out, Ab_out, B_out, Bb_out;
       
      lab3_mod I1(A_out, Ab_out, B_out, Bb_out, x_in, y_in, reset, clk);
     
      initial
        begin
               clk   = 1'b0;
               reset = 1'b0;     // initialized ff to reset state
          #15  reset = 1'b1;     //returns reset to low after circuit initialized  
         
          //After reset PS = 00
    /*
           Semplified State Table  
    PS  |  XY=  00  01  10  11
    AB  |       AB  AB  AB  AB
    ---------------------------
    00  |       11  01  10  00
    01  |       10  10  11  11
    10  |       01  01  01  01
    11  |       00  00  10  10

    */
          #20 {x_in, y_in} = 2'b00; //00>11
          #20 {x_in, y_in} = 2'b00; //11>00
         
          #20 {x_in, y_in} = 2'b00; //00>11
          #20 {x_in, y_in} = 2'b01; //11>00
          #20 {x_in, y_in} = 2'b01; //00>01
         
          #20 {x_in, y_in} = 2'b01; //01>10
          #20 {x_in, y_in} = 2'b01; //10>01
         
          #20 {x_in, y_in} = 2'b00; //01>10
          #20 {x_in, y_in} = 2'b00; //10>01
          #20 {x_in, y_in} = 2'b00; //01>10*
          #20 {x_in, y_in} = 2'b10; //10>01
          #20 {x_in, y_in} = 2'b00; //01>10
          #20 {x_in, y_in} = 2'b11; //10>01
         
          #20 {x_in, y_in} = 2'b10; //01>11
          #20 {x_in, y_in} = 2'b10; //11>10
          #20 {x_in, y_in} = 2'b10; //10>01
          #20 {x_in, y_in} = 2'b11; //01>11
          #20 {x_in, y_in} = 2'b11; //11>10
         
          #20 {x_in, y_in} = 2'b00; //10>01
          #20 {x_in, y_in} = 2'b10; //01>11
          #20 {x_in, y_in} = 2'b00; //11>00
          #20 {x_in, y_in} = 2'b11; //00>00
          #20 {x_in, y_in} = 2'b10; //00>10
          #20 {x_in, y_in} = 2'b00; //10>01
          #20 {x_in, y_in} = 2'b00; //01>10
       
        end
      always #10 clk = ~clk;
    endmodule

     
    Initially, all the #20 were #10. I was thinking i did not maintain the xy inputs long enough to get a proper output. That was not the case. Things were tracking along until the line with the * in the comments.

    First, is there an easier way test through a state table? Is there a more efficient way to building a test bench to test through the state table?
     
  2. jcsd
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