Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

Verilog Xilinx wont synthesize

  1. Oct 12, 2013 #1
    I am trying to build a BCD driver for my BASYS2 board that i can supply a 16bit data stream and will display the number on the four 7 segment LED.

    In this module, i have just hard coded the numbers to display. It does not currently have the 16bit input. It scans across each of the four 7 segment led and will display 1 2 3 4.

    The module tests fine in the test bench but when i go to synthesize it with the zilinx software, i get an Unsupported Control Statement error.

    I have read through my verilog book and everything seems to be in order.

    I have annotated the code where xilinx point to the issue.

    Here is the verilog code:

    Code (Text):

    module scanner(AN, BCD, segments, scan, clk);
      input wire clk;
      output reg [1:0] scan;
      output reg [3:0] AN;
      output reg [3:0] BCD;
      output reg [6:0] segments;
      initial scan = 2'b00;
          @(posedge clk)   //<<<<<<<Error points here
            scan = scan + 1'b1;
    //Turns on or off each of the 4 7 seg LEDs  
    // AN0 1 on,  0 off
    // AN1 1 off, 0 on
    // AN2 1 off, 0 on
    // AN3 1 on,  0 off
                             //LED     3210
                  2'b00 : AN <= 4'b0111;   //AN0 ON
                  2'b01 : AN <= 4'b0100;   //AN1 ON
                  2'b10 : AN <= 4'b0010;   //AN2 ON
                  2'b11 : AN <= 4'b1110;   //AN3 ON  
                  //Temp to give BCD input some values
                  2'b00 : BCD <= 4'b0100;  
                  2'b01 : BCD <= 4'b0011;  
                  2'b10 : BCD <= 4'b0010;
                  2'b11 : BCD <= 4'b0001;  
                  //Due to the physical FPGA 7 Seg LED, the segments is inverted
                  //to drive the correct segments on the display.
                  //                                abcdefg
                  4'b0000 : segments = 7'b0000001; //zero
                  4'b0001 : segments = 7'b1001111; //one
                  4'b0010 : segments = 7'b0010010; //two
                  4'b0011 : segments = 7'b0000110; //three
                  4'b0100 : segments = 7'b1001100; //four
                  4'b0101 : segments = 7'b0100100; //five
                  4'b0110 : segments = 7'b0100000; //six
                  4'b0111 : segments = 7'b0001111; //seven
                  4'b1000 : segments = 7'b0000000; //eight
                  4'b1001 : segments = 7'b0001100; //nine
                  4'b1010 : segments = 7'b0001000; //a
                  4'b1011 : segments = 7'b1100000; //b
                  4'b1100 : segments = 7'b0110001; //c
                  4'b1101 : segments = 7'b1000010; //d
                  4'b1110 : segments = 7'b0110000; //e
                  4'b1111 : segments = 7'b0111000; //f
                  default : segments = 7'b0110000; //e
  2. jcsd
  3. Oct 12, 2013 #2
    Found out that the @(posedge clk) needed to be before the begin...
  4. Oct 13, 2013 #3


    User Avatar
    Gold Member

    A good habit when writing synthesizable verilog is to use the standard flop template and to include a reset term.
    The reset term is most important for simulation (since everything starts as X and X+1 = X). The flops all start at zero in Xilinx unless you set them to 1 during the reset, but that's not true for simulation.

    Also, you should use nonblocking assignment (<=) for synchronous elements (flip-flops) or you will have huge simulation problems in the future and will be throwing around #1's to get your sim to work.
    Code (Text):

    //async reset flop
    always @ (posedge clk or posedge reset) begin
       if(reset == 1) begin
           scan <= 0;
       else begin
           scan <= scan+1;

    //sync reset flop
    always @ (posedge clk) begin
       if(reset == 1) begin
           scan <= 0;
       else begin
           scan <= scan+1;

Share this great discussion with others via Reddit, Google+, Twitter, or Facebook